Patents Examined by Sazzad Hossain
  • Patent number: 10768230
    Abstract: Embodiments are directed to a computer implemented method and system for the testing, characterization and diagnostics of integrated circuits. A system might include a device under test, such as an integrated circuit, that includes an adaptive microcontroller. The method includes loading a testing program for execution by the adaptive microcontroller, causing the microcontroller to execute the testing program. Once results from the testing program are received, the testing program can be adaptively modified based on the results. The modified testing program can be run again. The testing program can modify parameters of the integrated circuit that are not externally accessible. Other embodiments are also disclosed.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: September 8, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert M. Casatuta, Mary P. Kusko, Gary W. Maier, Franco Motika, Phong T. Tran
  • Patent number: 10746795
    Abstract: There is provided an integrated circuit comprising at least one logic path, comprising a plurality of sequential logic elements operably coupled into a scan chain to form at least one scan chain under test, at least one IR drop sensor operably coupled to the integrated circuit power supply, operable to output a first logic state when a sensed supply voltage is below a first predefined value and to output a second logic state when the sensed supply voltage is above the first predefined value, at least one memory buffer operably coupled to a scan test data load-in input and a scan test data output of the at least one scan chain under test, and control logic operable to gate logic activity including the scan shift operation inside the integrated circuit for a single cycle when the at least one IR drop sensor outputs the first logic state and to allow normal scan test flow when the at least one IR drop sensor outputs the second logic state.
    Type: Grant
    Filed: October 30, 2012
    Date of Patent: August 18, 2020
    Assignee: NXP USA, Inc.
    Inventors: Sergey Sofer, Asher Berkovitz, Michael Priel
  • Patent number: 10742238
    Abstract: Methods, systems, and devices for wireless communication are described. The examples described herein may enable a decoder to determine path metrics for various decoding paths based on identified frozen bit locations of a polar code. The path metric for a decoding path may be based on bit metrics determined for the identified frozen bit locations along the decoding path. Once the path metrics and bit metrics are determined, the decoder may compare these metrics to threshold criteria and determine whether to discard decoding paths based on the comparison. The techniques described herein for discarding decoding paths may allow the decoder to discard, prune, or disqualify certain decoding paths that are unlikely to provide an accurate representation of bits received from another device. Consequently, the decoder may be able to save power by terminating a decoding process early (i.e., early termination) if all paths are discarded, pruned, or disqualified.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: August 11, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Jamie Menjay Lin, Gabi Sarkis, Yang Yang
  • Patent number: 10720943
    Abstract: A data storage device may include: a storage configured to store user data, firmware and a boot code; and a controller configured to control data exchange with the storage, and comprising an error correction code (ECC) engine configured to perform error correction during the data exchange, wherein the ECC engine stores a first parity check matrix, performs error correction on data exchanged with the storage based on the first parity check matrix during a first operation mode, and performs error correction on data exchanged with the storage based on a second parity check matrix extracted from the firmware during a second operation mode.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: July 21, 2020
    Assignee: SK hynix Inc.
    Inventors: Jung Ae Kim, Jang Hyun Kim, Sung Jin Park
  • Patent number: 10699798
    Abstract: The present invention extends to methods, systems, and computer program products for testing storage device power circuitry. A storage device controller includes an embedded test program. The storage device controller executes the test program in response to receiving a test command. In one aspect, the test program issues a plurality of different command patterns to test shared power circuitry of storage device components (e.g., shared by an array of NAND flash memory devices). The test program identifies a command pattern that causes a greatest total current draw. In another aspect, the test program issues a specified command pattern (possibly repeatedly) to shared power circuitry to determine if the shared power circuitry fails.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: June 30, 2020
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Laura Marie Caulfield, Mark Alan Santaniello, J. Michael Andrewartha, John J. Siegler
  • Patent number: 10693598
    Abstract: The present disclosure provides a configuration method for sending and receiving data and an apparatus thereof, the method comprises receiving a first configuration signal sent from a network device by a terminal device, wherein, the first configuration signal is for indicating whether a first Transport Block to be sent by the network device is a retransmitted Transport Block, and the first configuration signal contains DCI information of the first Transport Block; receiving the first Transport Block sent from the network device by a terminal device, wherein, the first Transport Block comprises at least one Code Block Group; decoding the Code Block Group in the first Transport Block by a terminal device according to the DCI information of the first Transport Block. The technical scheme provided by the present disclosure has an advantage of greater correct rate of data transmission.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: June 23, 2020
    Assignee: YULONG COMPUTER TELECOMMUNICATION SCIENTIFIC (SHENZHEN) CO., LTD.
    Inventors: Mingju Li, Yunfei Zhang
  • Patent number: 10686560
    Abstract: Certain aspects of the present disclosure provide techniques and apparatus for quick radio link control (RLC) retransmission on hybrid automatic repeat request (HARQ) failure during tune away. According to certain aspects, a method for wireless communications is provided. The method generally includes performing communications with a base station (BS) using radio components tuned to a first air interface, detecting a tune-away of the radio components from the first air interface to a second air interface while performing the communications, and scheduling one or more packets for retransmission to the BS upon completion of the tune-away, wherein the one or more packets are one or more packets that failed to be transmitted due to the tune-away.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: June 16, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Gang Andy Xiao, Ashwini Raina, Shailesh Maheshwari, Rudhir Upretee, Mohan Krishna Gowda, Bao Vinh Nguyen, Deepak Krishnamoorthi, Prasad Kadiri, Pavan Kaivaram, Chintan Shirish Shah, Meric Uzunoglu, Aziz Gholmieh
  • Patent number: 10671478
    Abstract: A scrubbing controller of a semiconductor memory device includes a scrubbing address generator and a weak codeword address generator. The scrubbing address generator generates a scrubbing address for all codewords in a first bank array of a plurality of bank arrays in a first scrubbing mode. The scrubbing address is associated with a normal scrubbing operation and changes in response to an internal scrubbing signal and a scrubbing command. The weak codeword address generator generates a weak codeword address for weak codewords in the first bank array in a second scrubbing mode. The weak codeword address is associated with a weak scrubbing operation and is generated in response to the internal scrubbing signal.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: June 2, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Uhn Cha, Ye-Sin Ryu
  • Patent number: 10659194
    Abstract: This application relates to the field of wireless communications technologies, and discloses a polar code encoding method and apparatus, to improve accuracy of reliability calculation and ordering for polarized channels. The method includes: obtaining a first sequence used to encode K to-be-encoded bits, where the first sequence includes sequence numbers of N polarized channels, the sequence numbers of the N polarized channels are arranged in the first sequence based on reliability of the N polarized channels, K is a positive integer, N is a mother code length of a polar code, N is a positive integer power of 2, and K?N; selecting sequence numbers of K polarized channels from the first sequence in descending order of reliability; and placing the to-be-encoded bits based on the selected sequence numbers of the K polarized channels, and performing polar code encoding on the to-be-encoded bits.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: May 19, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Jun Wang, Gongzheng Zhang, Huazi Zhang, Chen Xu, Lingchen Huang, Shengchen Dai, Hejia Luo, Yunfei Qiao, Rong Li, Jian Wang, Ying Chen, Nikita Polianskii, Mikhail Kamenev, Zukang Shen, Yourui HuangFu, Yinggang Du
  • Patent number: 10649031
    Abstract: Hardware assisted high speed serial (HSS) transceiver testing including receiving, by a link layer hardware state machine on a HSS transmitting device, an instruction to generate a test pattern, wherein the test pattern comprises a sequence of data units; loading, by the link layer hardware state machine, each unique data unit into embedded random access memory (RAM); generating, by the link layer hardware state machine, the test pattern comprising the sequence of data units using the unique data units stored in the embedded RAM, wherein at least one of the unique data units is repeated in the sequence of data units of the test pattern; and sending, by the link layer hardware state machine, the generated test pattern to an input of a HSS transceiver.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: May 12, 2020
    Assignee: International Business Machines Corporation
    Inventors: Jeremy T. Ekman, Donald J. Ziebarth, George R. Zettles, IV, Trevor J. Timpane
  • Patent number: 10622077
    Abstract: A decoding method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The decoding method includes: reading first data from memory cells of the rewritable non-volatile memory module, wherein the first data includes a first bit stored in a first memory cell; obtaining a storage state of at least one second memory cell which is different from the first memory cell; obtaining first reliability information corresponding to the first bit according to the storage state of the second memory cell, wherein the first reliability information is different from default reliability information corresponding to the first bit; and decoding the first data according to the first reliability information. Therefore, a decoding efficiency can be improved.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: April 14, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Yu-Cheng Hsu, Szu-Wei Chen, Tien-Ching Wang
  • Patent number: 10608787
    Abstract: A wireless communication system, in which a redundancy bit is transmitted from a first communication device to a second communication device when the second communication device fails to decode the encoded bits, includes a processor. The processor selects communication patterns that respectively satisfy a requested quality, calculates, for each of the selected communication patterns, a transmission data length that indicates a length of the redundancy bit, calculates, for each of the selected communication patterns, a transmission latency between the first communication device and the second communication device based on the calculated transmission data length, and generates a retransmission parameter corresponding to a communication pattern with lowest transmission latency among the selected communication patterns.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: March 31, 2020
    Assignee: Mobile Techno Corp.
    Inventors: Satoshi Sonobe, Masanori Yofune, Atsuhiko Sugitani
  • Patent number: 10599504
    Abstract: The following description is directed to dynamically adjusting a refresh rate. In one example, a method can include determining a rate of memory errors, and dynamically adjusting a refresh rate of a memory based at least partially on the determined rate of memory errors.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: March 24, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Christopher James BeSerra, Gary S. Shankman, Gavin Akira Ebisuzaki, Terry Lee Nissley
  • Patent number: 10593418
    Abstract: Examples of the present disclosure provide apparatuses and methods related to performing comparison operations in a memory. An example apparatus might include a first group of memory cells coupled to a first access line and configured to store a first element. An example apparatus might also include a second group of memory cells coupled to a second access line and configured to store a second element. An example apparatus might also include sensing circuitry configured to compare the first element with the second element by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations without transferring data via an input/output (I/O) line.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: March 17, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Sanjay Tiwari
  • Patent number: 10567115
    Abstract: A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder which encodes input bits including outer encoded bits to generate an LDPC codeword including the input bits and parity bits to be transmitted to a receiver in a current frame; a puncturer which punctures a part of the parity bits which is not transmitted in the current frame; and an additional parity generator which selects at least a part of the parity bits to generate additional parity bits transmitted to the receiver in a previous frame of the current frame, wherein a number of the additional parity bits is determined based on a number of the outer encoded bits and a number of the parity bits left after the puncturing.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: February 18, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hong-sil Jeong, Kyung-joong Kim, Se-ho Myung
  • Patent number: 10551435
    Abstract: Systems and methods disclosed herein provide for an integrated circuit partitioned into a plurality of regions of a two-dimensional grid, wherein each region of the grid corresponds to similarly located scan flops. The systems and methods also provide for enabling clock gates to scan flops in some regions of the integrated circuit and disabling clock gates to other regions in order to better manage power dissipation during ATPG. Specifically, toggle disabling templates are applied during ATPG in order to enable clock gates in certain regions of the two-dimensional grid.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: February 4, 2020
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Nitin Parimi, Krishna Vijaya Chakravadhanula, Patrick Wayne Gallagher, Vivek Chickermane, Brian Edward Foutz
  • Patent number: 10545824
    Abstract: A system and method of performing selective error coding in memory management of a memory device are described. The method includes performing a process of detecting and correcting memory errors in the memory of the memory device either prior to or after a chip mark associated with the memory device is in place. The method also includes localizing hard errors of the memory device based on a second process of detecting the memory errors in the memory of the memory device, the hard errors being persistent memory errors that persist from the process of detecting and correcting the memory errors to the second process, determining an extent of the hard errors based on the localizing, and preventing placement of the chip mark or removing the chip mark after de-allocating one or more ranges of addresses based on a result of the determining the extent of the hard errors.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: January 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Diyanesh Babu Chinnakkonda Vidyapoornachary, Timothy J. Dell, Marc A. Gollub, Anil B. Lingambudi
  • Patent number: 10545819
    Abstract: An error management system for a data storage device can generate soft-decision log-likelihood ratios (LLRs) using multiple reads of memory locations. 0-to-1 and 1-to-0 bit flip count data provided by multiple reads of reference memory locations can be used to generate probability data that is used to generate possible LLR values for decoding target pages. Possible LLR values are stored in one or more look-up tables.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: January 28, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Guangming Lu
  • Patent number: 10547329
    Abstract: A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode outer-encoded bits to generate an LDPC codeword including LDPC information bits and parity bits; a puncturer configured to puncture some of the parity bits included in the LDPC codeword; and a mapper configured to map the LDPC codeword except the punctured parity bits to symbols for transmission to a receiver, wherein the puncturer calculates a number of parity bits to be punctured among the parity bits included in the LDPC codeword based on a number of the outer-encoded bits, a number of the LDPC information bits, and a minimum number of parity bits to be punctured among the parity bits included in the LDPC codeword.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: January 28, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Se-ho Myung, Kyung-Joong Kim, Hong-sil Jeong
  • Patent number: 10541709
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: January 21, 2020
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur