Abstract: A test mode signal is generated to include a test pattern and an error reporting sequence. The test mode signal is sent on link that includes one or more extension devices and two or more sublinks. The test mode signal is to be sent on a particular one of the sublinks and is to be used by a receiving device to identify errors on the particular sublink. The error reporting sequence is to be encoded with error information to describe error status of sublinks in the plurality of sublinks.

Abstract: In one embodiment, earphones with bimodally fitting earbuds enable accurate reproduction of music while exposing a wearer to environmental noises on one side of the wearer. More specifically, an open earbud is designed to create a substantially open (i.e., unsealed) sound chamber around one ear while a closed earbud is designed to create a substantially closed sound chamber around the other ear. Because the open earbud is associated with sound leakage that alters both the intended level and the bass content of the music, the earphones include a signal redistribution subsystem that perspicaciously replaces at least a portion of this lost signal energy. Advantageously, such earphones expose the wearer to useful localized sounds, such as noises from an auto lane adjacent to a bike lane, while conveying the intended mix of music more accurately than conventional earphones with two open earbuds.

Abstract: Systems and methods for string-based erase verify to create partial good blocks are disclosed. A block in non-volatile flash memory may include multiple strings. In practice, one string may be slower to erase than other strings. In analyzing the strings, the memory device may iteratively analyze the strings to verify as erased. As one example, the iterations are modified by changing which strings are erased in the subsequent iterations (e.g., only the strings that fail the erase verify). As another example, a predetermined number of iterations are performed after a majority of the strings are verified as erased. In this way, the strings verified as erased need not undergo more deep erasing, which may damage the strings. Further, if fewer than all of the strings are verified as erased, the memory device may designate the block as a partially good block.

Abstract: Techniques for improving the bit error rate (BER) performance of an error correction system are described. In an example, the error correction system implements low-density parity-check (LDPC) decoding that uses bit flipping. In a decoding iteration, a feature map is generated for a bit of an LDPC codeword. The bit corresponds to a variable node. The feature map is input to a neural network that is trained to determine whether bits should be flipped based on corresponding feature maps. An output of the neural network is accessed. The output indicates that the bit should be flipped based on the feature map. The bit is flipped in the decoding iteration based on the output of the neural network.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.

Abstract: A method to transport forward error correction (FEC) codes in a symbol encoded transmission stream includes encoding a data stream from a data source into data symbols using computing circuits, generating first FEC codes from the data symbols using the computing circuits, encoding the first FEC codes into first FEC symbols using the computing circuits, merging the data symbols and the first FEC symbols into the transmission stream using the computing circuits, and transmitting the merged transmission stream to a sink device using the computing circuits. The encoding of the data stream into the data symbols and the encoding of the first FEC codes into the first FEC symbols may include the same encoding technique.

Abstract: A data storage device with high security is disclosed. A nonvolatile memory provides a storage space divided into a plurality of first-level cells. The first-level cells are grouped into a plurality of second-level cells with each second-level cell containing several first-level cells. Each of the plurality of first-level cells is provided with checking and correcting code by a control unit. When reading a specified first-level cell, the control unit checks data in the specified first-level cell based on the checking and correcting code of the specified first-level cell and thereby performs a self-test on another space of a specified second-level cell. The specified first-level cell is provided in the specified second-level cell.

Abstract: At least a method and an apparatus are presented for determining a coded modulation scheme, the coded modulation scheme being defined by at least one non-binary error correcting code containing at least one non-binary parity-check equation, a modulation scheme, and a modulation mapping. Two or more candidate modulation mappings and two or more candidate parity-check equations are determined defining the at least one non-binary error correcting code, a candidate set comprising a candidate modulation mapping and at least one candidate parity-check equation providing codeword vectors and being associated with one or more metrics, each metric being evaluated for a number of distinct pairs of codeword vectors having an Euclidean distance of a defined value. One candidate modulation mapping and at least one candidate parity-check equation are selected according to an optimization criterion applied to the one or more metrics.

Abstract: A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword. The second memory is initialized to 0. The processor generates the LDPC codeword by performing accumulation with respect to the second memory using information bits. The accumulation is performed at parity bit addresses that are updated using a sequence corresponding to a parity check matrix (PCM).

Abstract: Techniques for improving the latency or processing performance of an error correction system are described. In an example, the error correction system implements LDPC decoding and uses an early termination rule to determine whether the LDPC decoding should be terminated prior to reaching a maximum number of iterations. The early termination rule involves various parameters that relate to the syndrome of the decoded LDPC codeword at each iteration. These parameters include the number of the current decoding iteration and the weight of the syndrome at the current iteration. For example, the early termination rule specifies that the LDPC decoding should be terminated prior to the maximum number of iterations either when the weight of the syndrome is zero, or when the current number of iterations reaches an iteration number threshold and the weight of the syndrome equals or exceeds a checksum threshold.

Abstract: Disclosed is system and method to implement an on-demand file repair protocol. In the protocol, a traffic source sends all data packets of a data file to a traffic sink. The traffic source then sends to the traffic sink an indication that the sending of the all data packets is complete. If data packets are missing, a request is received from the traffic sink for retransmission of missing packets. The traffic source then sends fountain codes of the missing packets to the traffic sink.

Abstract: An apparatus includes a memory and a controller. The memory may be configured to store data. The controller may be configured to process a plurality of input/output requests to a plurality of blocks of the memory that are not marked as bad on a block list, perform a code rate test that programs the plurality of blocks of the memory at three or more code rates of an error correction code scheme, and mark any of the plurality of blocks identified as bad during the code rate test on the block list.

Abstract: One embodiment of the present disclosure describes a memory system that may include one or more memory devices that may store data. The memory devices may receive command signals to access the stored data as a loopback signal. The memory devices may operate in a normal operational mode, a loopback operational mode, a retrieval operational mode, a non-inverting pass-through operational sub-mode, and an inverting pass-through operational sub-mode. The operational modes facilitate the transmission of the loopback signal for the purpose of monitoring of memory device operations. A selective inversion technique, which uses the operational modes, may protect the loopback signal integrity during transmission.

Abstract: A semiconductor memory device is provided to keep data reliability while decreasing programming time. A NAND flash memory loads programming data from an external input/output terminal to a page buffer/sense circuit. A detecting circuit for monitoring the programming data detects whether the programming data is a specific bit string. If it is detected that the programming data is not a specific bit string, a transferring/writing circuit transfers the programming data kept by the page buffer/sense circuit to an error checking correction (ECC) circuit, and an ECC code generated by an ECC operation is written to the page buffer/sense circuit. If it is detected that the programming data is a specific bit string, transfer of the programming data kept by the page buffer/sense circuit is forbidden and a known ECC code corresponding to the specific bit string is written to the page buffer/sense circuit.

Abstract: A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol.

Abstract: A transmitter, a receiver and methods of controlling the transmitter and the receiver are provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to generate an LDPC codeword by performing LDPC encoding on an L1 post signaling; a demux configured to demultiplex a plurality of bits constituting the L1 post signaling of the LDPC codeword; and a modulator configured to modulate the demultiplexed bits.

Abstract: A data communication method using forward error correction (FEC) includes: receiving at least one of symbols that constitute one encoding block unit; extracting information related to parameters that adjust an FEC encoding rate from the at least one symbol; determining whether an error may be corrected based on the extracted information related to the parameters and a number of symbols with errors from among the symbols that constitute the encoding block unit; and transmitting feedback information related to the symbols prior to the symbols that constitute the encoding block unit being completely received based on the determination of whether an error may be corrected.

Abstract: Apparatuses and methods for encoding, transmitting, receiving and decoding signal frames are provided. A transmitting apparatus includes: a frame encoder configured to perform Reed Solomon (RS) encoding on a plurality of frames in a vertical direction, wherein the frame encoder divides the plurality of frames into a plurality of groups, performs RS encoding for each group so that parities are added after the last frame of each group, and generates the RS-encoded frames. A receiver includes: a frame decoder configured to perform RS decoding on a plurality of received frames in a vertical direction, wherein the frame decoder divides the plurality of received frames into a plurality of groups, and performs RS decoding for each group to obtain information words without the parities.

Abstract: A first memory location stores circulant contents of portions A, C, E, and B of a parity check matrix H. A second memory location stores circulant column counts of the portions A, C, E, and B. A third memory location stores a dense matrix equal to (ET?1B+D)?1, where T is an identity matrix and D and T are also portions of the parity check matrix H. First and second parity information is generated in response to receiving information data. Generating the first and second parity information includes accessing the circular content of the portions A, C, E, and B of a parity check matrix H and accessing the circulant column counts of the portions A, C, E, and B.