Patents Examined by Scott B. Geyer
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Patent number: 10586700Abstract: A semiconductor structure includes a plurality of semiconductor fins on an upper surface of a semiconductor substrate. The semiconductor fins spaced apart from one another by a respective trench to define a fin pitch. A multi-layer electrical isolation region is contained in each trench. The multi-layer electrical isolation region includes an oxide layer and a protective layer. The oxide layer includes a first material on an upper surface of the semiconductor substrate. The protective layer includes a second material on an upper surface of the oxide layer. The second material is different than the first material. The first material has a first etch resistance and the second material has a second etch resistance that is greater than the first etch resistance.Type: GrantFiled: November 16, 2017Date of Patent: March 10, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael P. Belyansky, Richard A. Conti, Dechao Guo, Devendra K. Sadana, Jay W. Strane
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Patent number: 10573750Abstract: Methods of forming germanium channel structure are described. An embodiment includes forming a germanium fin on a substrate, wherein a portion of the germanium fin comprises a germanium channel region, forming a gate material on the germanium channel region, and forming a graded source/drain structure adjacent the germanium channel region. The graded source/drain structure comprises a germanium concentration that is higher adjacent the germanium channel region than at a source/drain contact region.Type: GrantFiled: December 24, 2015Date of Patent: February 25, 2020Assignee: Intel CorporationInventors: Glenn Glass, Karthik Jambunathan, Anand Murthy, Chandra Mohapatra, Seiyon Kim
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Patent number: 10559592Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate and a first alternating conductor/dielectric stack disposed on the substrate and a dielectric layer disposed over the first alternating conductor/dielectric stack. A second alternating conductor/dielectric stack is disposed on the dielectric layer. The NAND memory device includes one or more array common source contacts extending orthogonally with respect to the surface of the substrate through the first layer stack and the second layer stack, wherein at least one of the one or more array common source contacts includes a first conductive contact and a second conductive contact that is disposed over and electrically connected with the first conductive contact.Type: GrantFiled: September 10, 2018Date of Patent: February 11, 2020Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Jun Liu, Zongliang Huo
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Patent number: 10559656Abstract: Described herein are nanosheet-FET structures having a wrap-all-around contact where the contact wraps entirely around the S/D epitaxy structure, thereby increasing contact area and ultimately allowing for improved S/D contact resistance. Other aspects described include nanosheet-FET structures having an air gap as a bottom isolation area to reduce parasitic S/D leakage to the substrate.Type: GrantFiled: May 2, 2018Date of Patent: February 11, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Emilie M. S. Bourjot, Julien Frougier, Yi Qi, Ruilong Xie, Hui Zang, Hsien-Ching Lo, Zhenyu Hu
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Patent number: 10559593Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A first channel region containing a first semiconductor material and a second channel region containing a second semiconductor material are formed over a buried insulating layer of a silicon-on-insulator substrate. A first gate electrode of a first field-effect transistor is formed over the first channel region. A second gate electrode of a second field-effect transistor is formed over the second channel region. The first semiconductor material of the first channel region has a first germanium concentration. The second semiconductor material of the second channel region has a second germanium concentration that is greater than the first germanium concentration in the first semiconductor material of the first channel region.Type: GrantFiled: August 13, 2018Date of Patent: February 11, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Carsten Metze, Berthold Reimer, Simeon Morvan
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Patent number: 10559720Abstract: An LED includes a gallium nitride substrate, a first semiconductor layer disposed thereon, and a mesa including a second semiconductor layer disposed on the first semiconductor layer and an intervening active layer. A first contact layer includes an outer contact part in contact with the first semiconductor layer near an edge of the substrate and an inner contact part in contact with the first semiconductor layer within a region encompassed by the outer contact part. A second contact layer is disposed on the mesa in contact with the second semiconductor layer. An upper insulation layer has first and second opening parts overlapping the first and second contact layers. First and second electrode pads are electrically connected to the first and second contact layers through the first and second opening parts. The LED can be driven at 150-315 A/cm2 and has a maximum junction temperature of 150-190° C.Type: GrantFiled: August 10, 2018Date of Patent: February 11, 2020Assignee: Seoul Viosys Co., Ltd.Inventors: Jong Min Jang, Seon Min Bae, Jae Hee Lim, Chang Yeon Kim, Chae Hon Kim
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Patent number: 10553725Abstract: A vertical stack transistor includes: a first transistor and a second transistor, located in a vertical direction, wherein the first transistor includes a first gate electrode, a first insulating layer, a first electrode, a first channel, and a second electrode, which are sequentially stacked in the vertical direction, and the second transistor includes a second gate electrode, a second insulating layer, a third electrode, a second channel, and a fourth electrode, which are sequentially stacked in the vertical direction, wherein the second gate electrode and the second electrode are the same electrode.Type: GrantFiled: August 10, 2018Date of Patent: February 4, 2020Assignees: Samsung Display Co., Ltd., Chung Ang University Industry Academic Cooperation FoundationInventors: Tae Young Kim, Jong Woo Park, Hyuck-In Kwon, Dae-Hwan Kim, Hee-Joong Kim, Sae-Young Hong
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Patent number: 10553675Abstract: In accordance with an embodiment of an integrated circuit, a cavity is buried in a semiconductor body below a first surface of the semiconductor body. An active area portion of the semiconductor body is arranged between the first surface and the cavity. The integrated circuit further includes a trench isolation structure configured to provide a lateral electric isolation of the active area portion.Type: GrantFiled: October 17, 2017Date of Patent: February 4, 2020Assignee: Infineon Technologies AGInventors: Sebastian Schmidt, Donald Dibra, Oliver Hellmund, Peter Irsigler, Andreas Meiser, Hans-Joachim Schulze, Martina Seider-Schmidt, Robert Wiesner
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Patent number: 10553478Abstract: Embodiments of the present disclosure may provide a method of forming an integrated circuit (IC) structure, the method including: forming a doped metal layer within a contact opening in an inter-level dielectric (ILD) material on a conductive region, such that the doped metal layer overlies the conductive region, the doped metal layer including a first metal doped with a second metal; and forming a contact to the conductive region within the contact opening of the ILD material by annealing the doped metal layer such that the second metal diffuses into the ILD material to form an interface liner directly between the annealed doped metal layer and the ILD material, the interface liner formed only on sidewalls of the contact opening and in direct contact with the ILD material and only at an interface of the doped metal layer and the ILD material.Type: GrantFiled: July 30, 2018Date of Patent: February 4, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Xunyuan Zhang, Moosung M. Chae
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Patent number: 10553639Abstract: A solid-state imaging device includes: a first electrode formed above a semiconductor substrate; a photoelectric conversion film formed on the first electrode and for converting light into signal charges; a second electrode formed on the photoelectric conversion film; a charge accumulation region electrically connected to the first electrode and for accumulating the signal charges converted from the light by the photoelectric conversion film; a reset gate electrode for resetting the charge accumulation region; an amplification transistor for amplifying the signal charges accumulated in the charge accumulation region; and a contact plug in direct contact with the charge accumulation region, comprising a semiconductor material, and for electrically connecting to each other the first electrode and the charge accumulation region.Type: GrantFiled: August 22, 2018Date of Patent: February 4, 2020Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Yusuke Sakata, Mitsuyoshi Mori, Yutaka Hirose, Hiroshi Masuda, Hitoshi Kuriyama, Ryohei Miyagawa
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Patent number: 10547024Abstract: A display device is provided. The display device includes a display panel including first and second display substrates that face each other, having an overlap area in which the first and second display substrates overlap with each other, and having a protruding area on one side of the overlap area, a sealing member between the first and second display substrates along edges of the overlap area, and at least one chamfered portion including a first chamfered portion, which is formed on at least one side of the protruding area, and a second chamfered portion, which is formed on the overlap area and adjacent to the first chamfered portion, wherein in the second chamfered portion, an end of the first display substrate is positioned beyond an end of the second display substrate.Type: GrantFiled: April 13, 2018Date of Patent: January 28, 2020Assignee: Samsung Display Co., Ltd.Inventors: Hyun Min Hwang, Yong Kyu Jang, Jae Kyung Go, Dong Jo Kim, Young Min Kim, Chan Young Park, Dong Won Han
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Patent number: 10541190Abstract: An apparatus is described that includes a first semiconductor die. A second semiconductor die is stacked on the first semiconductor die. The first semiconductor die has a larger surface area than the second semiconductor die such that there exists a peripheral region of the first semiconductor die that is not covered by the second semiconductor die. The apparatus includes thermally conductive material above the second semiconductor die. The apparatus includes a compound mold between the thermally conductive material and both the second semiconductor die and the peripheral region of the first semiconductor die. The apparatus includes a thermally conductive structure extending through the compound mold that thermally couples the peripheral region to the thermally conductive material.Type: GrantFiled: November 30, 2015Date of Patent: January 21, 2020Assignee: Intel CorporationInventors: Chandra Jha, Eric Li
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Patent number: 10541192Abstract: Microfeature workpieces having alloyed conductive structures, and associated methods are disclosed. A method in accordance with one embodiment includes applying a volume of material to a bond pad of a microfeature workpiece, with the volume of material including a first metallic constituent and the bond pad including a second constituent. The method can further include elevating a temperature of the volume of material while the volume of material is applied to the bond pad to alloy the first metallic constituent and the second metallic constituent so that the first metallic constituent is alloyed generally throughout the volume of material. A thickness of the bond pad can be reduced from an initial thickness T1 to a reduced thickness T2.Type: GrantFiled: July 24, 2017Date of Patent: January 21, 2020Assignee: Micron Technology, Inc.Inventors: Warren M. Farnworth, Rick C. Lake, William M. Hiatt
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Patent number: 10529500Abstract: The present invention provides a method (201) for making composite materials used in making flexible supercapacitor prototype (106). The method (201) comprises the steps of rolling the exfoliated graphite (101) using rolling instrument (103) to form an EG sheet (104). In-situ coating is done on EG sheet (104) to form flexible EG or polymer electrode which is used to make supercapacitors (106). A graphite powder (101) is added with the mixture of HNO3 and H2SO4 in the ratio of 1:3 resulting in oxidized graphite. Oxidized graphite undergoes thermal shock in an isothermal furnace at a temperature of 900 degree Celsius for time duration of 2 minutes resulting in EG worms (102). These EG worms are rolled using a rolling instrument (103) to form an EG sheet (104).Type: GrantFiled: August 6, 2018Date of Patent: January 7, 2020Inventor: Venkataramana Gedela
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Patent number: 10530038Abstract: A semiconductor package device includes a substrate, an antenna and a conductor. The substrate has an upper surface. The antenna is disposed on the upper surface of the substrate. The conductor is disposed on the upper surface of the substrate and surrounds the antenna. The conductor has a first surface facing toward the antenna and a second surface opposite to the first surface. The second surface of the conductor is spaced apart from the upper surface of the substrate.Type: GrantFiled: March 6, 2018Date of Patent: January 7, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Shao-En Hsu, Huei-Shyong Cho, Shih-Wen Lu
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Patent number: 10529826Abstract: A method includes forming an active layer, forming a gate structure above a channel region of the active layer, forming a sidewall spacer adjacent the gate structure, forming a first dielectric layer adjacent the sidewall spacer, recessing the gate structure to define a gate cavity, forming an inner spacer in the gate cavity, forming a cap layer in the gate cavity, recessing the first dielectric layer and the sidewall spacer to expose sidewall surfaces of the cap layer, removing the inner spacer to define a first spacer cavity, forming an upper spacer in the spacer cavity and contacting sidewall surfaces of the cap layer, forming a second dielectric layer above the upper spacer and the cap layer, and forming a first contact structure at least partially embedded in the second dielectric layer and contacting a surface of the upper spacer.Type: GrantFiled: August 13, 2018Date of Patent: January 7, 2020Assignee: GLOBALFOUNDRIES Inc.Inventors: Julien Frougier, Ruilong Xie, Chanro Park, Kangguo Cheng
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Patent number: 10522599Abstract: A foldable, flexible display apparatus includes a flexible display panel which displays an image and includes a display side on which the image is displayed and of which portions thereof face each other in a folded state of the flexible display apparatus; a cover window on the display side of the flexible display panel and including: a window film comprising a transparent plastic film having a modulus of elasticity of about 6.3 gigapascals or more; and a coating layer on the window film, and configured to be transparent and to protect the window film from physical damage thereto; and an adhesive layer between the window film and the display side of the flexible display panel, and configured to have elasticity and bond the window film and the flexible display panel to each other.Type: GrantFiled: September 10, 2018Date of Patent: December 31, 2019Assignee: Samsung Display Co., Ltd.Inventors: Yong-Cheol Jeong, Seung-Wook Nam, So-Yeon Han, Kyu-Young Kim, Ah-Young Kim, Gui-Nam Min, Kyu-Taek Lee
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Patent number: 10522561Abstract: Embodiments of a method for forming a three-dimensional (3D) memory devices are disclosed. The method can comprise forming a device wafer including: forming a first channel hole penetrating a first alternating layer stack of a device wafer, forming an epitaxial layer on a bottom of the first channel hole, and forming a first channel layer on a sidewall of the first channel hole. The method can further comprise forming at least one connecting wafer, each connecting wafer including a second channel hole penetrating a second alternating layer stack without an epitaxial layer on a bottom of the second channel hole; and bonding the at least one connecting wafer and the device wafer, such that a second channel layer on a sidewall of the second channel hole in each connecting wafer is electrically connected with the first channel layer in the device wafer.Type: GrantFiled: July 27, 2018Date of Patent: December 31, 2019Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Kun Zhang, Fandong Liu, Zhiliang Xia
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Patent number: 10522397Abstract: A miniaturized transistor is provided. A first layer is formed over a third insulator over a semiconductor; a second layer is formed over the first layer; an etching mask is formed over the second layer; the second layer is etched using the etching mask until the first layer is exposed to form a third layer; a selective growth layer is formed on a top surface and a side surface of the third layer; the first layer is etched using the third layer and the selective growth layer until the third insulator is exposed to form a fourth layer; and the third insulator is etched using the third layer, the selective growth layer, and the fourth layer until the semiconductor is exposed to form a first insulator.Type: GrantFiled: March 15, 2019Date of Patent: December 31, 2019Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yuta Endo, Hideomi Suzawa, Sachiaki Tezuka, Tetsuhiro Tanaka, Toshiya Endo, Mitsuhiro Ichijo
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Patent number: 10522438Abstract: A package structure includes a redistribution layer, a chip, an encapsulant, a plurality of under ball release layers, and a plurality of solder balls. The redistribution layer includes a first surface, a second surface opposite to the first surface, and a patterned circuit layer, wherein the patterned circuit layer includes a plurality of pads protruding from the first surface. The chip is disposed on the second surface and electrically connected to the patterned circuit layer. The encapsulant is disposed on the second surface and encapsulates the chip. The under ball release layers cover the pads respectively. The solder balls are disposed on the under ball release layers and electrically connected to the pads.Type: GrantFiled: May 16, 2017Date of Patent: December 31, 2019Assignee: Industrial Technology Research InstituteInventors: Chun-Yi Cheng, Wei-Yuan Cheng, Shu-Wei Kuo, Yu-Jhen Yang
