Abstract: A flexible multilayer construction (1000) for mounting a plurality of light emitting semiconductor devices (LESDs 100, 110, 120) includes a flexible dielectric substrate (200) comprising top (210) and bottom (220) major surfaces, and pluralities of corresponding electrically conductive top (300, 310, 320, 330) and bottom (500, 510, 520, 530) pads disposed on the top and bottom major surfaces, respectively. An electrically conductive via (400, 410, 420, 430) connects each pair of corresponding top and bottom pads, a side of each top pad partially overlapping a side of the corresponding bottom pad and a side of the substrate, such that in a plan view, each top pad fully overlaps the corresponding bottom pad.

Abstract: Provided is a display device having a flexible substrate including an active region and a wiring region. The active region possesses a plurality of pixels each including a display element. The wiring region has a plurality of terminals, and a plurality of wirings extends from the active region to the plurality of terminals. An insulating film included in the active region and extending from the active region has a sidewall between an edge of the flexible substrate and the wiring adjacent to the edge in the wiring region. The sidewall has a curved portion on a plane in which the plurality of wirings is arranged, and a distance between the edge and the curved portion is curvedly varied.

Abstract: A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies and a package substrate carrying the first and second semiconductor dies. The second semiconductor die includes a first peripheral portion extending laterally outward beyond a first edge surface of the first semiconductor die. Similarly, the package substrate includes a second peripheral portion extending laterally outward beyond a second edge surface of the second semiconductor die. The semiconductor die assembly further includes a first volume of molded underfill material between the first and second semiconductor dies, a second volume of molded underfill material between the package substrate and the second semiconductor die, a first molded peripheral structure laterally adjacent to the first edge surface of the first semiconductor die, and a second molded peripheral structure laterally adjacent to the second edge surface of the second semiconductor die.

Abstract: A semiconductor device has a first substrate and a second substrate. An opening is formed through the second substrate. A first semiconductor component and second semiconductor component are disposed between the first substrate and second substrate. The second substrate is electrically coupled to the first substrate through the first semiconductor component. A first terminal of the first semiconductor component is electrically coupled to the first substrate. A second terminal of the first semiconductor component is electrically coupled to the second substrate. The second semiconductor component extends into the opening. An encapsulant is deposited over the first substrate and second substrate.

Abstract: When a film thickness of a second epitaxial film is measured, an infrared light is irradiated from a surface side of the second epitaxial film onto a base layer on which a first epitaxial film and the second epitaxial film are formed. A reflected light from an interface between the first epitaxial film and the base layer and a reflected light from a surface of the second epitaxial film are measured to obtain a two-layer film thickness, which is a total film thickness of the first epitaxial film and the second epitaxial film. The film thickness of the second epitaxial film is calculated by subtracting a one-layer film thickness, which is a film thickness of the first epitaxial film, from the two-layer film thickness.

Abstract: Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.

Abstract: In an embodiment, a package includes: a first redistribution structure; a first integrated circuit die connected to the first redistribution structure; a ring-shaped substrate surrounding the first integrated circuit die, the ring-shaped substrate connected to the first redistribution structure, the ring-shaped substrate including a core and conductive vias extending through the core; a encapsulant surrounding the ring-shaped substrate and the first integrated circuit die, the encapsulant extending through the ring-shaped substrate; and a second redistribution structure on the encapsulant, the second redistribution structure connected to the first redistribution structure through the conductive vias of the ring-shaped substrate.

Abstract: Aspects of the present disclosure are directed to systems and methods to reduce inductance on an integrated circuit package of a memory sub-system. A memory sub-system is also hereinafter referred to as a “memory device.” An example of a memory sub-system is a storage system, such as a SSD, and can be embodied as an integrated circuit package, including but not limited to a pin grid array (PGA), and ball grid array (BGA).

Abstract: Related fields of the present disclosure are in the field of transistor devices, and in particular, FinFET device structures formed using aspect ratio trapping trench (ART) process techniques. For example, a FinFET device consistent with the present disclosure comprises a first fin structure including a first upper fin portion atop a first lower fin portion and a second fin structure including a second upper fin portion atop a second lower fin portion. The first and second upper fin structures include a Group IV material and the first and second lower fin structures include a Group III-V material.

Abstract: Various embodiments of a modular unit for a topologic qubit and of scalable quantum computing architectures using such modular units are disclosed herein. For example, one example embodiment is a modular unit for a topological obit comprising 6 Majorana zero modes (MZMs) on a mesoscopic superconducting island. These units can provide the computational MZMs with protection from quasiparticle poisoning. Several possible realizations of these modular units are described herein. Also disclosed herein are example designs for scalable quantum computing, architectures comprising the modular units together with gates and reference arms (e.g., quantum dots, Majorana wires, etc.) configured to enable joint parity measurements to be performed for various combinations of two or four MZMs associated with one or two modular units, as well as other operations on the states of MZMs.

Abstract: A switching element includes a lower barrier electrode on a substrate, a switching pattern on the lower barrier electrode, and an upper barrier electrode on the switching pattern. The lower barrier electrode includes a first lower barrier electrode layer, and a second lower barrier electrode layer interposed between the first lower barrier electrode layer and the switching pattern and whose density is different from the density of the first lower barrier electrode.

Abstract: A semiconductor device package includes a substrate, a heat dissipation structure disposed on the substrate, and a first optical module disposed on the heat dissipation structure. The heat dissipation structure includes a housing, an optical component disposed on the housing, and a light-emitting device disposed in the housing and capable of emitting light toward the first optical component.

Abstract: A device is disclosed that includes an active layer, a gate structure positioned above a channel region of the active layer and a first sidewall spacer positioned adjacent the gate structure. The device also includes a gate cap layer positioned above the gate structure and an upper spacer that contacts sidewall surfaces of the gate cap layer, a portion of an upper surface of the gate structure and an inner surface of the first sidewall spacer.

Abstract: A power semiconductor arrangement includes a carrier and packages. Each package: encloses a power semiconductor die having first and second load terminals and configured to conduct a die load current between the load terminals; has a package body with a top side, a footprint side and sidewalls extending from the footprint side to the top side; a lead frame structure configured to electrically and mechanically couple the package to the carrier with the package footprint side facing the carrier, the lead frame structure including at least one first outside terminal electrically connected with the first load terminal of the die; a top layer arranged at the package top side and electrically connected with the second load terminal of the die. A top heatsink is attached to each package top layer, electrically contacted to each package top layer, and configured to conduct at least a sum of the die load currents.

Abstract: A gate driver integrated circuit is provided. The gate driver integrated circuit includes a substrate having a drift region of a first doping type therein, and a field effect transistor including a drain region of the first doping type, a source region of the first doping type, and a gate structure. The gate driver integrated circuit also includes a first well region of a second doping type and a first contact region of the second doping type. Each of the first well region and the drain region is formed in the drift region, the source region is formed in the first well region, and an end portion of the gate structure near the source region covers a portion of the first well region. Further, the gate driver integrated circuit includes a field plate structure formed on the substrate and disposed between the source region and the drain region.

Abstract: A wafer-level packaging method includes providing a base substrate and providing first chips. A photolithographic bonding layer is formed on the base substrate or on the first chips. First vias are formed in the photolithographic bonding layer. The first chips are pre-bonded to the base substrate through a photolithographic bonding layer with each first chip corresponding to a first via. A thermal compression bonding process is used to bond the first chips to the base substrate such that an encapsulation material fills between adjacent first chips and covers the first chips and the base substrate. The base substrate is etched to form second vias through the base substrate with each second via connected to a first via to form a first conductive via. A first conductive plug is formed in the first conductive via to electrically connect to a corresponding first chip.

Abstract: Provided herein is a capacitor, and method for forming a capacitor, comprising an anode, a dielectric over the anode; a cathode over the dielectric; and the cathode comprises core shell particles.

Abstract: A light emitting device for a display includes a substrate and first, second, and third LED sub-units, a first transparent electrode between the first and second LED sub-units and in ohmic contact with the first LED sub-unit, a second transparent electrode between the second and third LED sub-units and in ohmic contact with the second LED sub-unit, a third transparent electrode between the second transparent electrode and the third LED sub-unit and in ohmic contact with the third LED sub-unit, at least one current spreader connected to at least one of the first, second, and third LED sub-units, electrode pads disposed on the substrate, and through-hole vias formed through the substrate, in which at least one of the through-hole vias is formed through the substrate and the first and second LED sub-units.

Abstract: Provided is a nonaqueous lithium-type power storage element in which a lithium compound is included in positive electrode, wherein energy loss due to voltage decrease under high temperatures and high voltages is reduced, and the high-load charge and discharge cycle characteristics are exceptional.

Abstract: An asymmetrically shaped chip-scale packaging (CSP) light-emitting device (LED) includes an LED chip, a photoluminescent structure (or a light-transmitting structure), and a reflective structure. The photoluminescent structure covers the upper surface and/or the edge surface of the LED chip; and the reflective structure at least partially covers the edge surface of the photoluminescent structure. The reflective structure partially reflects the primary light emitted from the edge surface of the LED chip or the converted secondary light radiated from the edge surface of the photoluminescent structure, therefore shaping the radiation pattern asymmetrically.