Abstract: A system for processing data may include a plurality of storage resources coupled to a backplane, a storage controller coupled to the backplane and configured to couple to an information handling system. The storage controller may configured to implement, using single-root input/output virtualization a first virtual function allocated to a first set of one or more of the plurality of storage resources and allocated to a software-defined storage virtual machine executing on a hypervisor of the information handling system and one of a physical function and a second virtual function allocated to a second set of one or more of the plurality of storage resources and allocated to the hypervisor.

Abstract: A system and method for performing copy offload operations. When a copy offload operation from a first volume (pointing to a first medium) to a second volume (pointing to a second medium) is requested, the copy offload operation is performed without accessing the data being copied. A third medium is created, and the first medium is recorded as the underlying medium of the third medium. The first volume is re-pointed to the third medium. Also, a fourth medium is created, the second volume is re-pointed to the fourth medium, and the second medium is recorded as the underlying medium of the targeted range of the fourth medium. All other ranges of the fourth medium have the second medium as their underlying medium.

Abstract: A method, computer program product, and computer system for receiving, by a computing device, an IO request. It may be determined that data of the IO request includes an indication of an attribute. A prefix descriptor may be constructed for the data in a self-descriptive page buffer based upon, at least in part, determining that the data of the IO request includes the indication of the attribute. An appropriate Application Programming Interface (API) may be called to process the IO request based upon, at least in part, the prefix descriptor.

Abstract: A device connected by a link to a host system can include a first port to receive a capability configuration message across a link and a message request receiving logic comprising hardware circuitry to identify a capability of the device identified in the capability configuration message, determine that the capability is to be presented or hidden from operation based on a capability hide enable bit in the capability configuration message, and configure a capability linked list to present or hide the capability based on the determination. The device can also include a message response generator logic comprising hardware circuitry to generate a response message indicating that the capability is to be presented or hidden from operation. The device can include a second port to transmit the response message across the link.

Abstract: An input/output store instruction is handled. A data processing system includes a system nest coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to at least one external device which is coupled to the at least one input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed. The asynchronous core-nest interface includes an input/output status array with multiple input/output status buffers. The system firmware includes a retry buffer and the core includes an analysis and retry logic.

Abstract: An apparatus and method for processing non-maskable interrupt source information. For example, one embodiment of a processor comprises: a plurality of cores comprising execution circuitry to execute instructions and process data; local interrupt circuitry comprising a plurality of registers to store interrupt-related data including non-maskable interrupt (NMI) data related to a first NMI; and non-maskable interrupt (NMI) processing mode selection circuitry, responsive to a request, to select between at least two NMI processing modes to process the first NMI including: a first NMI processing mode in which the plurality of registers are to store first data related to a first NMI, wherein no NMI source information related to a source of the NMI is included in the first data, and a second NMI processing mode in which the plurality of registers are to store both the first data related to the first NMI and second data comprising NMI source information indicating the NMI source.

Abstract: A SPI master may configure a set of hardware registers associated with a SPI client with a set of communication parameters. The SPI master may send a message to the SPI client. The SPI master may periodically ping the SPI client until the SPI master receives an acknowledgement message from the SPI client in response to the message from the SPI master. The SPI master may periodically ping the SPI client based upon the set of communication parameters. The SPI client may transmit the acknowledgement message to the SPI master based upon the set of communication parameters. The SPI master may receive the acknowledgement message from the SPI client. The SPI master may determine a status of a read operation or a write operation associated with the message based upon the acknowledgement message.

Abstract: An arithmetic unit performs store-to-load forwarding based on predicted dependencies between store instructions and load instructions. In some embodiments, the arithmetic unit maintains a table of store instructions that are awaiting movement to a load/store unit of the instruction pipeline. In response to receiving a load instruction that is predicted to be dependent on a store instruction stored at the table, the arithmetic unit causes the data associated with the store instruction to be placed into the physical register targeted by the load instruction. In some embodiments, the arithmetic unit performs the forwarding by mapping the physical register targeted by the load instruction to the physical register where the data associated with the store instruction is located.

Abstract: A circuit device includes first and second physical layer circuits, a bus switch circuit that switches connection between a first bus and a second bus, which are compliant with the USB standard, ON in a first period and OFF in a second period, and a processing circuit that performs processing for transferring a packet in a transfer route constituted by the first bus, the first and second physical layer circuits, and the second bus, in the second period. The second physical layer circuit includes a disconnection detection circuit that detects device disconnection of a device connected to the second bus side. If device disconnection is detected in the second period, the connection between the first bus and the second bus is switched from off to on after a wait period has elapsed from the timing at which the device disconnection was detected.

Abstract: Systems and methods for managing optimized branching in executable instructions are disclosed. In one implementation, a processing device may identify, in a sequence of executable instructions, a jump instruction associated with a safe static key. Responsive to determining that a condition is satisfied, the processing device may further replace the jump instruction with an optimized transfer of control instruction provided by one of: a no operation instruction or an unconditional jump instruction specifying a first jump target location. Responsive to determining that a rate of modification of the safe static key exceeds a threshold rate, the processing device may also replace the optimized transfer of control instruction with a conditional jump instruction specifying the first jump target location.

Abstract: A data storage system can employ multiple concurrent domains with data storage devices each having a single data port. The data storage system may connect a number of hosts to a data storage device via a network controller, an expander, and an expander module with the data storage device having a single data port. A first data domain and a second data domain are each established from the network controller to the data storage device with the first data domain being independent of the second data domain. At least one illegal loop can be identified between the first data domain and the second data domain with the expander module and subsequently corrected with the expander as directed by the expander module.

Abstract: This application relates to transfer of digital audio data between a host device and an accessory apparatus that may be connected to the host device via a suitable connector, such as a USB connector. A path selector is operable to establish either a first digital data path or a second digital data path for transfer of digital data. The first digital data path includes a first data bus host and a general purpose digital data interface suitable for bulk data transfer between the first data bus host and the applications processor of the device. This may be a default USB path. The second digital data path includes a second data bus host and at least one pair of second path data interfaces. The second data bus host does not form part of the applications processor and each of said second path data interfaces comprises a digital audio interface suitable for streaming of audio data.

Abstract: A virtualization platform for Network Functions Virtualization (NFV) is provided. The virtualization platform may include a host processor coupled to an acceleration coprocessor. The acceleration coprocessor may be a reconfigurable integrated circuit to help provide improved flexibility and agility for the NFV. The coprocessor may include multiple virtual function hardware acceleration modules each of which is configured to perform a respective accelerator function. A virtual machine running on the host processor may wish to perform multiple accelerator functions in succession at the coprocessor on a given data. In one suitable arrangement, intermediate data output by each of the accelerator functions may be fed back to the host processor. In another suitable arrangement, the successive function calls may be chained together so that only the final resulting data is fed back to the host processor.

Abstract: A group of transistors is configured to drive a bus at time slots, to express data on the bus. The group of transistors dissipates an amount of electrical energy when driving the bus to a logic level opposite to a logic level present on the bus in an immediate preceding time slot. The group of transistors is arranged to dump another amount of electrical energy. Dumping of the other amount of electrical energy is responsive to driving the bus to a logic level that is the same as present on the bus in an immediate preceding time slot. The dumped amount of electrical energy is equivalent to the amount of energy dissipated by the transistors when transitioning the bus to a different logic level. Other aspects are also described.

Abstract: An electronic meeting tool and method for recording a meeting. The method includes the steps of coupling a display node to at least one base node of at least one communications network, displaying data transmitted to the at least one base node from processing devices coupled to the at least one communications network on the display node during a meeting; and recording and storing digitally the data transmitted during the meeting and written on the whiteboard to provide a record of the meeting.

Abstract: The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.

Abstract: In one embodiment, a condition monitoring circuit can include a circuit controller and a node. The node can include a gate controller, a node controller and one or more gates. The node can be configured to detachably couple to a bus of a monitoring system associated with an industrial machine. The circuit controller can be configured to identify an operating parameter associated with the industrial machine. The gate controller can be configured to transfer, via the one or more gates, one or more data packets including data characterizing the operating parameter from the bus in the monitoring system. The one or more gates can be configured to prevent transfer of an outgoing data packet to the bus via the node.

Abstract: A data analysis system to analyze data. The data analysis system includes a data buffer configured to receive data to be analyzed. The data analysis system also includes a state machine lattice. The state machine lattice includes multiple data analysis elements and each data analysis element includes multiple memory cells configured to analyze at least a portion of the data and to output a result of the analysis. The data analysis system includes a buffer interface configured to receive the data from the data buffer and to provide the data to the state machine lattice.

Abstract: Embodiments are provided herein for component composition of a disaggregated computing system. A plurality of general purpose links connecting a computing element to other hardware elements are provided within the disaggregated computing system. Each of the plurality of general purpose links comprise a point-to-point connection to at least one of the other hardware elements such that the plurality of general purpose links conform to a configuration used by the other hardware elements regardless of a type of data being transferred through the plurality of general purpose links.

Abstract: Apparatuses and methods for input receiver circuits and receiver masks for electronic memory are disclosed. Embodiments of the disclosure include memory receiver masks having shapes other than rectangular shapes. For example, a receiver mask according to some embodiments of the disclosure may have a hexagonal shape. Other shapes of receiver masks may also be included in other embodiments of the disclosure. Circuits, timing, and operating parameters for achieving non-rectangular and various shapes of receiver mask are described.