Abstract: An LED package structure for increasing heat-dissipating and light-emitting efficiency includes a substrate unit, an alloy unit, a light-emitting unit, a conductive unit and a package unit. The substrate unit has a substrate body, a first conductive pad, a second conductive pad and a chip-placing pad. The alloy unit has a Ni/Pd alloy formed on the chip-placing pad. The light-emitting unit has an LED chip positioned on the Ni/Pd alloy of the alloy unit by solidified solder ball or glue. The conductive unit has two conductive wires, and the LED chip is electrically connected to the first conductive pad and the second conductive pad by the two conductive wires, respectively. The package unit has a light-transmitting package gel body formed on the top surface of the substrate body in order to cover the light-emitting unit and the conductive unit.

Abstract: An LED semiconductor body includes a number of at least two radiation-generating active layers. Each active layer has a forward voltage, wherein the number of active layers is adapted to an operating voltage in such a way that the voltage dropped across a series resistor connected in series with the active layers is at most of the same magnitude as a voltage dropped across the LED semiconductor body. The invention furthermore describes various uses of the LED semiconductor body.

Abstract: A semiconductor device includes: a semiconductor chip mounting substrate, a control circuit board, a power terminal holder and a semi-fixing member. The semiconductor chip mounting substrate includes a substrate, a semiconductor chip provided on a first major surface of the substrate, and a first and second semiconductor chip connection electrodes. The control circuit board is provided generally in parallel to the first major surface and includes a control circuit, a control signal terminal connected to the control circuit, and a through hole extending in a direction generally perpendicular to the first major surface. The power terminal holder is provided on opposite side of the control circuit board from the semiconductor chip mounting substrate and includes a power terminal. The semi-fixing member includes a shank portion and an end portion. The shank portion is fixed to the power terminal holder and penetrates through the through hole.

Abstract: A method for providing a pressure sensor substrate comprises creating a first cavity that extends inside the substrate in a first direction perpendicular to a main surface of the substrate, and that extends inside the substrate, in a second direction perpendicular to the first direction, into a first venting area of the substrate; creating a second cavity that extends in the first direction inside the substrate, that extends in parallel to the first cavity in the second direction, and that does not extend into the first venting area; and opening the first cavity in the first venting area.

Abstract: An integrated circuit die stack including a first integrated circuit die mounted upon a substrate, the first die including pass-through vias (‘PTVs’) composed of conductive pathways through the first die with no connection to any circuitry on the first die; and a second integrated circuit die, identical to the first die, shifted in position with respect to the first die and mounted upon the first die, with the PTVs in the first die connecting signal lines from the substrate through the first die to through silicon vias (‘TSVs’) in the second die composed of conductive pathways through the second die connected to electronic circuitry on the second die; with the TSVs and PTVs disposed upon each identical die so that the positions of the TSVs and PTVs on each identical die are translationally compatible with respect to the TSVs and PTVs on the other identical die.

Abstract: There is provided a light emitting module. The light emitting module includes: a semiconductor light emitting element that emits light; and a plate-like optical wavelength conversion member that converts a wavelength of light emitted from the semiconductor light emitting element and emits light having the converted wavelength. The semiconductor light emitting element and the optical wavelength conversion member are directly bonded to each other.

Abstract: An interconnection between a sublithographic-pitched structure and a lithographic pitched structure is formed. A plurality of conductive lines having a sublithographic pitch may be lithographically patterned and cut along a line at an angle less than 45 degrees from the lengthwise direction of the plurality of conductive lines. Alternately, a copolymer mixed with homopolymer may be placed into a recessed area and self-aligned to form a plurality of conductive lines having a sublithographic pitch in the constant width region and a lithographic dimension between adjacent lines at a trapezoidal region. Yet alternately, a first plurality of conductive lines with the sublithographic pitch and a second plurality of conductive lines with the lithographic pitch may be formed at the same level or at different.

Abstract: A method includes preparing a cover member; preparing an image pickup element including a substrate including a pixel region including a plurality of photo detectors on a principal surface, a first concavo-convex portion including a plurality of first convex portions configured to concentrate light on the plurality of photo detectors, the first convex portions each having a lens shape, and a second concavo-convex portion surrounding the first concavo-convex portion, the second concavo-convex portion including a plurality of second convex portions; and fixing the cover member to a region of the image pickup element using a fixing member, the region being between the first concavo-convex portion and the second concavo-convex portion.

Abstract: To provide a Schottky electrode in a diamond semiconductor, which has a good adhesion properties to diamonds, has a contacting surface which does not become peeled due to an irregularity in an external mechanical pressure, does not cause a reduction in yield in a diode forming process and does not cause deterioration in current-voltage characteristics, and a method of manufacturing the Schottky electrode. A Schottky electrode which includes: scattered island-form pattern Pt-group alloy thin films which are formed on a diamond surface formed on a substrate, in which the Pt-group alloy includes 50 to 99.9 mass % of Pt and 0.

Abstract: Organic anti-stiction coatings such as, for example, hydrocarbon and fluorocarbon based self-assembled organosilanes and siloxanes applied either in solvent or via chemical vapor deposition, are selectively etched using a UV-Ozone (UVO) dry etching technique in which the portions of the organic anti-stiction coating to be etched are exposed simultaneously to multiple wavelengths of ultraviolet light that excite and dissociate organic molecules from the anti-stiction coating and generate atomic oxygen from molecular oxygen and ozone so that the organic molecules react with atomic oxygen to form volatile products that are dissipated, resulting in removal of the exposed portions of the anti-stiction coating. A hybrid etching process using heat followed by UVO exposure may be used. A shadow mask (e.g., of glass or quartz), a protective material layer, or other mechanism may be used to selective expose the portions of the anti-stiction coating to be UVO etched.

Abstract: The invention relates to a field effect transistor comprising at least one source electrode layer and at least one drain electrode layer arranged in the same plane, a semiconductor layer, an insulator layer and a gate electrode layer, wherein the gate electrode layer, as seen perpendicular to the plane of the at least one source electrode layer and the at least one drain electrode layer, only partly covers a channel arranged between the at least one source electrode layer and the at least one drain electrode layer.

Abstract: Methods and systems for electrochemically depositing doped metal oxide and metal chalcogenide films are disclosed. An example method includes dissolving a metal precursor into a solution, adding a halogen precursor to the solution, and applying a potential between a working electrode and a counter electrode of an electrochemical cell to deposit halogen doped metal oxide or metal chalcogenide onto a substrate. Another example method includes dissolving a zinc precursor into a solution, adding an yttrium precursor to the solution, and applying a potential between a working electrode and a counter electrode of an electrochemical cell to deposit yttrium doped zinc oxide onto a substrate. Other embodiments are described and claimed.

Abstract: An LED semiconductor body includes a number of at least two radiation-generating active layers. Each active layer has a forward voltage, wherein the number of active layers is adapted to an operating voltage in such a way that the voltage dropped across a series resistor connected in series with the active layers is at most of the same magnitude as a voltage dropped across the LED semiconductor body. The invention furthermore describes various uses of the LED semiconductor body.

Abstract: A standard cell includes a capacity element which is made up of a first well diffusion layer into which a first conductive impurity is diffused in a region from a surface of a substrate to a predetermined depth, an insulation film which is provided on the first well diffusion layer, and a first dummy pattern which is provided on the insulation film.

Abstract: A method that includes forming a first layer having a first dopant concentration, the first layer having an integrated circuit region and a micro-electromechanical region and doping the micro-electromechanical region of the first layer to have a second dopant concentration is presented. The method includes forming a second layer having a third dopant concentration overlying the first layer, doping the second layer that overlies the micro-electromechanical region to have a fourth dopant concentration, forming a micro-electromechanical structure in the micro-electromechanical region using the first and second layers, and forming active components in the integrated circuit region using the second layer.

Abstract: A thermionic electron emitter/collector includes a substrate and a doped diamond electron emitter/collector layer on the substrate. The doped diamond electron emitter/collector layer has at least a first and a second doping concentration as a function of depth such that the first doping concentration is different from the second doping concentration.

Abstract: A dual gate of a semiconductor device includes a semiconductor substrate divided into a cell region with a recessed gate forming area and a peripheral region with PMOS and NMOS forming areas; first and second conductive type SiGe layers, the first conductive type SiGe layer being formed over the cell region and the PMOS forming area of the peripheral region, and the second conductive type SiGe layer being formed over the NMOS forming area of the peripheral region; first and second conductive type polysilicon layers, the first conductive type polysilicon layer being formed over the first conductive type SiGe layer and the second conductive type polysilicon layer being formed over the second conductive type SiGe layer; and a metallic layer and a hard mask layer stacked over the first and second conductive type polysilicon layers.

Abstract: When a thin semiconductor device is formed by grinding a wafer, it has been necessary to dice the wafer into dies and process the back surfaces of the dies separately. In the invention, a wafer 2a is half-diced from the front surface thereof to form groove portions 4 therein, and in this state, the front surface of the wafer 2a is attached to a supporting body 5 having rigidity with an adhesive layer 6. Then, the wafer 2a is ground from the back surface and diced into individual dies 2b, and then a back surface process including a heat treatment such as the formation of back surface electrodes 9a is performed in the state where the dies 2b are attached to the supporting body 5.

Abstract: A light emitting device includes a substrate, a first cladding layer, an active layer, and a second cladding layer formed in that order, and a reflective part formed above the substrate and separated from the active layer. At least a portion of the active layer constitutes a plurality of gain regions, which forms at least one gain region pair, a first gain region of which is provided in one direction and a second gain region is provided in another direction different from the one direction. At least a portion of an end surface of the first gain region and the second gain region overlap with each other. Light emitted from the end surface of the first gain region is reflected by the reflective part, and propagates in the same direction or in the focusing direction with light emitted from the end surface of the second gain region.

Abstract: A semiconductor memory device having a first wiring layer which is provided on a first insulator, and which extends in a first direction, and a non-volatile memory cell which is provided in a pillar shape on the first wiring layer, and which includes a non-ohmic element and variable resistance element connected in series. The resistance value of the variable resistance element changes in accordance with a voltage or current applied thereto. A barrier layer is provided on the memory cell and is configured in an in-plane direction. A conductive layer is provided on the barrier layer and is configured in an in-plane direction. A second insulator is provided on the first insulator and covers side surfaces of the memory cell, the barrier layer, and the conductive layer. A second wiring layer is provided on the conductive layer and extends in a second direction.