Abstract: A light emitting device includes a substrate, and a plurality of light emitting structures disposed thereon. Each of the light emitting structures includes an auxiliary electrode disposed on the substrate, a first insulating layer disposed on the substrate and covering the auxiliary electrode, an electrode disposed on the first insulating layer, a second insulating layer disposed on the first insulating layer and having a first opening exposing the electrode, an organic light emitting layer disposed in the first opening, a cathode disposed on the organic light emitting layer, at least a conductive structure penetrating through the first insulating layer and the second insulating layer, and a closed ring structure disposed on the second insulating layer and around the cathode, wherein a thickness of the closed ring structure is larger than that of the cathode.

Abstract: A method that includes forming a first layer having a first dopant concentration, the first layer having an integrated circuit region and a micro-electromechanical region and doping the micro-electromechanical region of the first layer to have a second dopant concentration is presented. The method includes forming a second layer having a third dopant concentration overlying the first layer, doping the second layer that overlies the micro-electromechanical region to have a fourth dopant concentration, forming a micro-electromechanical structure in the micro-electromechanical region using the first and second layers, and forming active components in the integrated circuit region using the second layer.

Abstract: Cross-coupling between a gate conductor and an active region of a semiconductor substrate is provided by forming a gate dielectric layer on the semiconductor substrate and lithographically patterning the gate dielectric layer to form opening therein over a portion of the active region at which electrical contact with the gate conductor is desired. After implanting electrical dopants, a gate conductor layer is deposited and patterned. A remaining portion of the gate conductor layer includes an integral conductor structure, which includes a first portion overlying a gate dielectric over an active region and a second portion contacting the semiconductor material of the same active region or a different active region. The gate dielectric layer can be deposited within gate cavities in planarization dielectric material layer in a replacement gate scheme, or can be deposited on planar surfaces of active regions and/or shallow trench isolation structures in a gate first processing scheme.

Abstract: An integrated circuit die stack including a first integrated circuit die mounted upon a substrate, the first die including pass-through vias (‘PTVs’) composed of conductive pathways through the first die with no connection to any circuitry on the first die; and a second integrated circuit die, identical to the first die, shifted in position with respect to the first die and mounted upon the first die, with the PTVs in the first die connecting signal lines from the substrate through the first die to through silicon vias (‘TSVs’) in the second die composed of conductive pathways through the second die connected to electronic circuitry on the second die; with the TSVs and PTVs disposed upon each identical die so that the positions of the TSVs and PTVs on each identical die are translationally compatible with respect to the TSVs and PTVs on the other identical die.

Abstract: A GaN-containing semiconductor light emitting device includes: an n-type semiconductor layer formed of GaN-containing semiconductor, an active layer formed on the n-type semiconductor layer, formed of GaN-containing semiconductor, and having a multiple quantum well structure including a plurality of barrier layers and well layers stacked alternately, and a p-type semiconductor layer formed on the active layer and formed of GaN-containing semiconductor, wherein: the barrier layers comprise: a first barrier layer disposed nearest to the n-type semiconductor layer among the barrier layers and formed of a GaN/AlGaN layer, and second barrier layers disposed nearer to the p-type semiconductor layer than the first barrier layer and including an InGaN/GaN layer which has a layered structure of a InGaN sublayer and a GaN sublayer; and the well layers are each formed of an InGaN layer having a narrower band gap than that in the InGaN sublayer.

Abstract: An organic light emitting display apparatus and method of manufacturing the organic light emitting display apparatus including a lower substrate having power lines in a non-display region that is outside a display region whereon an image is realized; and a functional layer formed between the power lines and an encapsulation substrate.

Abstract: An image sensor includes first pixels, second pixels and a deep trench. The first pixels are formed in an active region of a semiconductor substrate, and configured to measure photo-charges corresponding to incident light. The second pixels are formed in an optical-black region of the semiconductor substrate, and are configured to measure black levels. The deep trench is formed vertically in a boundary region of the optical-black region, where the boundary region is adjacent to the active region, and configured to block leakage light and diffusion carriers from the active region.

Abstract: A visually seamless method of joining a first piece of metal and a second piece of metal is described. The first piece of metal is placed in contact with an edge of the second piece of metal. In some embodiments, the edge includes a sacrificial lip. The first piece of metal forming a junction area with the edge of the second piece of metal, applying a forging force to the first piece of metal, the forging force having an effect of creating an extremely tight fit up between the first and the second pieces of metal, welding the first and the second pieces to form an assembly and forming a cosmetically enhancing protective layer on the surface of the assembly, the protective layer obscuring any visible artifacts on the surface of the assembly, the obscured visible artifacts including any discoloration or discontinuity created by the laser welding.

Abstract: An LED lamp (A1) includes a plurality of LEDs (2), a retainer (1) on which the light LEDs (2) are mounted, and a wiring pattern formed on the retainer (1) and electrically connected to the LEDs (2). The retainer (1) includes a plurality of substrates (11, 12, 15). Of the plurality of substrates (11, 12, 15), two adjacent substrates (11, 12) are connected to each other by a pair of bendable connection members (32a, 32b). The two substrates (11, 12) are arranged in such a manner that their normal line directions differ from each other.

Abstract: A display substrate includes a pixel electrode, an m-th data line (‘m’ is a natural number), a floating electrode, a (m+1)-th data line and a storage electrode. The pixel electrode is disposed in a pixel area of the substrate. The m-th data line is disposed at a first side of the pixel electrode and electrically connected to the pixel electrode. The floating electrode partially overlaps with the m-th data line. The (m+1)-th data line is disposed at a second side of the pixel electrode. The storage electrode is spaced apart from the (m+1)-th data line.

Abstract: An OLED device includes a thin film transistor including an active layer, a gate bottom electrode, a gate top electrode, an insulating layer covering the gate electrode, and a source electrode and a drain electrode on the insulating layer contacting the active layer; an organic light-emitting device electrically connected to the thin film transistor and including a sequentially stacked pixel electrode, on the same layer as the gate bottom electrode, emissive layer, and, opposite electrode, a pad bottom electrode on the same layer as the gate bottom electrode and a pad top electrode pattern on the same layer as the gate top electrode, the pad top electrode pattern including openings exposing the pad bottom electrode, and an insulation pattern covering the upper surface of the pad top electrode pattern on the same layer as the insulating layer, on an upper surface of the pad bottom electrode.

Abstract: Lateral collection architecture for a photodetector is achieved by depositing electrically conducting SLS layers onto a planar substrate and diffusing dopants of a carrier type opposite that of the layers through the layers at selected regions to disorder the superlattice and create diode junctions oriented transversely to the naturally enhanced lateral mobility of photogenerated charge carriers within the superlattice. The diode junctions are terminated at a top surface of the photodetector within an SLS layer of wide bandgap material to minimize unwanted currents. A related architecture disorders the superlattice of topmost SLS layers by diffusing therethrough a dopant configured as a grid and penetrating to a lower SLS layer having the same carrier type as the dopant and opposite that of the topmost layers to isolate pixels within the topmost layers. Ohmic contacts may be deposited on doped regions, pixels, and substrate to provide desired external connections.

Abstract: Thinned and highly reliable light emitting elements are provided. Further, light emitting devices in which light emitting elements are formed over flexible substrates are manufactured with high yield. One light emitting device includes a flexible substrate, a light emitting element formed over the flexible substrate, and a resin film covering the light emitting element, and in the light emitting element, an insulating layer serving as a partition has a convex portion and the convex portion is embedded in the resin film, that is, the resin film covers an entire surface of the insulating layer and an entire surface of the second electrode, whereby the light emitting element can be thinned and highly reliable. In addition, a light emitting device can be manufactured with high yield in a manufacturing process thereof.

Abstract: The present disclosure provides for multiple gate dielectric semiconductor structures and methods of forming such structures. In one embodiment, a method of forming a semiconductor structure includes providing a substrate including a pixel array region, an input/output (I/O) region, and a core region. The method further includes forming a first gate dielectric layer over the pixel array region, forming a second gate dielectric layer over the I/O region, and forming a third gate dielectric layer over the core region, wherein the first gate dielectric layer, the second gate dielectric layer, and the third gate dielectric layer are each formed to be comprised of a different material and to have a different thickness.

Abstract: A semiconductor device includes a semiconductor substrate having a diode active region and an edge termination region adjacent to each other, a first region of a first conductivity type in the diode active region, a second region of a second conductivity type, a third region of the first conductivity type in the edge termination region, and a fourth region of the second conductivity type. The first region and the third region share a drift region of the first conductivity type. The first region and the third region share a fifth region of the first conductivity type. The drift region in the third region is greater in number of crystal defects per unit volume than the drift region in the first region in order that the drift region in the third region is shorter in carrier lifetime than the drift region in the first region.

Abstract: Method for producing an insulation layer between a first electrode and a second electrode in a trench of a semiconductor body, wherein the method comprises the following features: providing a semiconductor body with a trench formed therein, wherein a first electrode is formed in a lower part of the trench, producing an insulation layer on the first electrode and at the sidewalls of the trench in an upper part of the trench in such a way that the insulation layer is formed in a U-shaped fashion in the trench, producing a protective layer on the insulation layer at least at the bottom of the remaining void in the trench, removing the insulation layer at the sidewalls of the trench in the upper part of the trench, removing the protective layer, producing a second electrode at least on the insulation layer above the first electrode.

Abstract: There is provided manufacturing method of a spark plug that includes a center electrode and a ground electrode with a discharge gap left therebetween. At least one of the center electrode and the ground electrode has an electrode body containing a base metal and a noble metal tip welded to the electrode body. The spark plug manufacturing method includes a laser welding step for welding the noble metal tip and the electrode body by placing the noble metal tip at a given position on the electrode body, irradiating a pulsed laser onto the noble metal tip and the electrode body and thereby sequentially forming welding spots corresponding to pulses of the laser in a circumferential direction of the noble metal tip, wherein at least one of the laser pulses is an initially increasing type laser pulse having a laser intensity waveform in which a laser intensity increases with time during a predetermined initial period from a pulse start time.

Abstract: An array structure solves issues that exist in conventional compound semiconductor photodiode arrays, such as large cross talk, large surface leaks, large stray capacitance, narrow detection wavelength bands, and bad manufacturing yield, simultaneously. A photodiode array has, laminated upon a semiconductor substrate, a buffer layer (8) with a broad forbidden band width, an I-type (low concentration photosensitive layer (2) with a narrow forbidden band width, and an n-type semiconductor window layer (3) with a broad forbidden band width, wherein photodiode elements are electrically separated from adjacent elements, by doping the periphery of the p-type impurity, and the detection wavelength band is expanded, by making the n-type window layer (3) on the photosensitive layer (2) a thinner layer with crystal growth.

Abstract: Light-emitting devices, and related components, systems and methods are disclosed.

Abstract: A method of bonding wafers with an aluminum-germanium bond includes forming an aluminum layer on a first wafer, and a germanium layer on a second wafer, and implanting the germanium layer with non-germanium atoms prior to forming a eutectic bond at the aluminum-germanium interface. The wafers are aligned to a desired orientation and the two layers are held in contact with one another. The aluminum-germanium interface is heated to a temperature that allows the interface of the layers to melt, thus forming a bond. A portions of the germanium layer may be removed from the second wafer to allow infrared radiation to pass through the second wafer to facilitate wafer alignment.