Patents Examined by Scott R. Wilson
  • Patent number: 8698189
    Abstract: An OLED device includes a thin film transistor including an active layer, a gate bottom electrode, a gate top electrode, an insulating layer covering the gate electrode, and a source electrode and a drain electrode on the insulating layer contacting the active layer; an organic light-emitting device electrically connected to the thin film transistor and including a sequentially stacked pixel electrode, on the same layer as the gate bottom electrode, emissive layer, and, opposite electrode, a pad bottom electrode on the same layer as the gate bottom electrode and a pad top electrode pattern on the same layer as the gate top electrode, the pad top electrode pattern including openings exposing the pad bottom electrode, and an insulation pattern covering the upper surface of the pad top electrode pattern on the same layer as the insulating layer, on an upper surface of the pad bottom electrode.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: April 15, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sun Park, Jong-Hyun Park, Yul-Kyu Lee, Kyung-Hoon Park, Sang-Ho Moon
  • Patent number: 8698172
    Abstract: Thinned and highly reliable light emitting elements are provided. Further, light emitting devices in which light emitting elements are formed over flexible substrates are manufactured with high yield. One light emitting device includes a flexible substrate, a light emitting element formed over the flexible substrate, and a resin film covering the light emitting element, and in the light emitting element, an insulating layer serving as a partition has a convex portion and the convex portion is embedded in the resin film, that is, the resin film covers an entire surface of the insulating layer and an entire surface of the second electrode, whereby the light emitting element can be thinned and highly reliable. In addition, a light emitting device can be manufactured with high yield in a manufacturing process thereof.
    Type: Grant
    Filed: January 4, 2010
    Date of Patent: April 15, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiro Katayama, Shingo Eguchi, Yoshiaki Oikawa, Ami Nakamura, Satoshi Seo, Kaoru Hatano
  • Patent number: 8698158
    Abstract: A display substrate includes a pixel electrode, an m-th data line (‘m’ is a natural number), a floating electrode, a (m+1)-th data line and a storage electrode. The pixel electrode is disposed in a pixel area of the substrate. The m-th data line is disposed at a first side of the pixel electrode and electrically connected to the pixel electrode. The floating electrode partially overlaps with the m-th data line. The (m+1)-th data line is disposed at a second side of the pixel electrode. The storage electrode is spaced apart from the (m+1)-th data line.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: April 15, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Myung-Koo Hur, Sang-Gun Choi
  • Patent number: 8697554
    Abstract: Lateral collection architecture for a photodetector is achieved by depositing electrically conducting SLS layers onto a planar substrate and diffusing dopants of a carrier type opposite that of the layers through the layers at selected regions to disorder the superlattice and create diode junctions oriented transversely to the naturally enhanced lateral mobility of photogenerated charge carriers within the superlattice. The diode junctions are terminated at a top surface of the photodetector within an SLS layer of wide bandgap material to minimize unwanted currents. A related architecture disorders the superlattice of topmost SLS layers by diffusing therethrough a dopant configured as a grid and penetrating to a lower SLS layer having the same carrier type as the dopant and opposite that of the topmost layers to isolate pixels within the topmost layers. Ohmic contacts may be deposited on doped regions, pixels, and substrate to provide desired external connections.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: April 15, 2014
    Assignee: Teledyne Scientific & Imaging, LLC
    Inventors: William E. Tennant, Gerard J. Sullivan, Mark Field
  • Patent number: 8698290
    Abstract: An LED lamp (A1) includes a plurality of LEDs (2), a retainer (1) on which the light LEDs (2) are mounted, and a wiring pattern formed on the retainer (1) and electrically connected to the LEDs (2). The retainer (1) includes a plurality of substrates (11, 12, 15). Of the plurality of substrates (11, 12, 15), two adjacent substrates (11, 12) are connected to each other by a pair of bendable connection members (32a, 32b). The two substrates (11, 12) are arranged in such a manner that their normal line directions differ from each other.
    Type: Grant
    Filed: November 6, 2009
    Date of Patent: April 15, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Tatsuya Masumoto, Satoru Masaki, Hironobu Kaneko
  • Patent number: 8685820
    Abstract: The present disclosure provides for multiple gate dielectric semiconductor structures and methods of forming such structures. In one embodiment, a method of forming a semiconductor structure includes providing a substrate including a pixel array region, an input/output (I/O) region, and a core region. The method further includes forming a first gate dielectric layer over the pixel array region, forming a second gate dielectric layer over the I/O region, and forming a third gate dielectric layer over the core region, wherein the first gate dielectric layer, the second gate dielectric layer, and the third gate dielectric layer are each formed to be comprised of a different material and to have a different thickness.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: April 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao-Hui Tseng, Dun-Nian Yaung, Jen-Cheng Liu, Wen-I Hsu, Min-Feng Kao
  • Patent number: 8686469
    Abstract: A semiconductor device includes a semiconductor substrate having a diode active region and an edge termination region adjacent to each other, a first region of a first conductivity type in the diode active region, a second region of a second conductivity type, a third region of the first conductivity type in the edge termination region, and a fourth region of the second conductivity type. The first region and the third region share a drift region of the first conductivity type. The first region and the third region share a fifth region of the first conductivity type. The drift region in the third region is greater in number of crystal defects per unit volume than the drift region in the first region in order that the drift region in the third region is shorter in carrier lifetime than the drift region in the first region.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: April 1, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventor: Katsumi Nakamura
  • Patent number: 8637367
    Abstract: Method for producing an insulation layer between a first electrode and a second electrode in a trench of a semiconductor body, wherein the method comprises the following features: providing a semiconductor body with a trench formed therein, wherein a first electrode is formed in a lower part of the trench, producing an insulation layer on the first electrode and at the sidewalls of the trench in an upper part of the trench in such a way that the insulation layer is formed in a U-shaped fashion in the trench, producing a protective layer on the insulation layer at least at the bottom of the remaining void in the trench, removing the insulation layer at the sidewalls of the trench in the upper part of the trench, removing the protective layer, producing a second electrode at least on the insulation layer above the first electrode.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: January 28, 2014
    Assignee: Infineon Technologies AG
    Inventor: Martin Poelzl
  • Patent number: 8633418
    Abstract: There is provided manufacturing method of a spark plug that includes a center electrode and a ground electrode with a discharge gap left therebetween. At least one of the center electrode and the ground electrode has an electrode body containing a base metal and a noble metal tip welded to the electrode body. The spark plug manufacturing method includes a laser welding step for welding the noble metal tip and the electrode body by placing the noble metal tip at a given position on the electrode body, irradiating a pulsed laser onto the noble metal tip and the electrode body and thereby sequentially forming welding spots corresponding to pulses of the laser in a circumferential direction of the noble metal tip, wherein at least one of the laser pulses is an initially increasing type laser pulse having a laser intensity waveform in which a laser intensity increases with time during a predetermined initial period from a pulse start time.
    Type: Grant
    Filed: March 27, 2008
    Date of Patent: January 21, 2014
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Tomoaki Kato, Akikazu Taido, Yuichi Nakano
  • Patent number: 8610170
    Abstract: An array structure solves issues that exist in conventional compound semiconductor photodiode arrays, such as large cross talk, large surface leaks, large stray capacitance, narrow detection wavelength bands, and bad manufacturing yield, simultaneously. A photodiode array has, laminated upon a semiconductor substrate, a buffer layer (8) with a broad forbidden band width, an I-type (low concentration photosensitive layer (2) with a narrow forbidden band width, and an n-type semiconductor window layer (3) with a broad forbidden band width, wherein photodiode elements are electrically separated from adjacent elements, by doping the periphery of the p-type impurity, and the detection wavelength band is expanded, by making the n-type window layer (3) on the photosensitive layer (2) a thinner layer with crystal growth.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: December 17, 2013
    Assignee: Irspec Corporation
    Inventors: Katsuhiko Nishida, Mutsuo Ogura
  • Patent number: 8513692
    Abstract: Light-emitting devices, and related components, systems and methods are disclosed.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: August 20, 2013
    Assignee: Luminus Devices, Inc.
    Inventors: Alexei A. Erchak, Elefterios Lidorikis, Chiyan Luo
  • Patent number: 8507913
    Abstract: A method of bonding wafers with an aluminum-germanium bond includes forming an aluminum layer on a first wafer, and a germanium layer on a second wafer, and implanting the germanium layer with non-germanium atoms prior to forming a eutectic bond at the aluminum-germanium interface. The wafers are aligned to a desired orientation and the two layers are held in contact with one another. The aluminum-germanium interface is heated to a temperature that allows the interface of the layers to melt, thus forming a bond. A portions of the germanium layer may be removed from the second wafer to allow infrared radiation to pass through the second wafer to facilitate wafer alignment.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: August 13, 2013
    Assignee: Analog Devices, Inc.
    Inventors: Thomas Kieran Nunan, Changhan Yun, Christine H. Tsau
  • Patent number: 8508008
    Abstract: In a semiconductor device, optical signal transfer capabilities are implemented on the basis of silicon-based monolithic opto-electronic components in combination with an appropriate waveguide. Thus, in complex circuitries, such as microprocessors and the like, superior performance may be obtained in terms of signal propagation delay, while at the same time thermal requirements may be less critical.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: August 13, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Uwe Griebenow, Sven Beyer, Thilo Sheiper, Jan Hoentschel
  • Patent number: 8501572
    Abstract: The present disclosure provides a bipolar junction transistor (BJT) device and methods for manufacturing the BJT device. In an embodiment, the BJT device includes: a semiconductor substrate having a collector region, and a material layer disposed over the semiconductor layer. The material layer has a trench therein that exposes a portion of the collector region. A base structure, spacers, and emitter structure are disposed within the trench of the material layer. Each spacer has a top width and a bottom width, the top width being substantially equal to the bottom width.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: August 6, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Tsung Kuo, Shih-Chang Liu, Chia-Shiung Tsai
  • Patent number: 8502268
    Abstract: A LDMOS structure includes a gate, a source, a drain and a bulk. The gate includes a polycrystalline silicon layer, the source includes a P-implanted layer, the drain includes the P-implanted layer, a P-well layer, and a deep P-well layer. A bulk terminal is connected through the P-implanted layer, the P-well layer, the deep P-well layer, and a P-type buried layer to the bulk. The LDMOS structure is able to be produced without any extra masking step, and it has compact structure, low on-resistance, and is able to withstand high current and high voltage.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: August 6, 2013
    Assignee: IPGoal Microelectronics (SiChuan) Co., Ltd.
    Inventor: Rongwei Yu
  • Patent number: 8487397
    Abstract: An integrated circuit with a self-aligned contact includes a substrate with a transistor formed thereover, a dielectric spacer, a protection barrier, and a conductive layer. The transistor includes a mask layer and a pair of insulating spacers formed on opposite sides of the mask layer. The dielectric spacer partially covers at least one of the insulating spacers of the transistor. The protection barrier is formed over the dielectric spacer. The conductive layer is formed over the mask layer, the protection barrier, the dielectric spacer, the insulating spacer and the dielectric spacer as a self-aligned contact for contacting a source/drain region of the transistor.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: July 16, 2013
    Assignee: Nanya Technology Corporation
    Inventors: Jar-Ming Ho, Yi-Nan Chen, Hsien-Wen Liu
  • Patent number: 8476637
    Abstract: Nanostructure array optoelectronic devices are disclosed. The optoelectronic device may have a top electrical contact that is physically and electrically connected to sidewalls of the array of nanostructures (e.g., nanocolumns). The top electrical contact may be located such that light can enter or leave the nanostructures without passing through the top electrical contact. Therefore, the top electrical contact can be opaque to light having wavelengths that are absorbed or generated by active regions in the nanostructures. The top electrical contact can be made from a material that is highly conductive, as no tradeoff needs to be made between optical transparency and electrical conductivity. The device could be a solar cell, LED, photo-detector, etc.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: July 2, 2013
    Assignee: Sundiode Inc.
    Inventors: James C. Kim, Sungsoo Yi, Danny E. Mars
  • Patent number: 8471353
    Abstract: A mesa photodiode which includes a mesa, the side wall of the mesa (a light-receiving region mesa) and at least a shoulder portion of the mesa in an upper face of the mesa are continuously covered with a semiconductor layer of a first conductivity type, a second conductivity type, a semi-insulating type, or an undoped type (an undoped InP layer, for example) that is grown on the side wall and the upper face of the mesa. In the semiconductor layer, a layer thickness D1 of a portion covering the side wall of the mesa is equal to or greater than 850 nm.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: June 25, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Tomoaki Koi, Isao Watanabe, Takashi Matsumoto
  • Patent number: 8461630
    Abstract: A conductive film to be a gate electrode, a first insulating film to be a gate insulating film, a semiconductor film in which a channel region is formed, and a second insulating film to be a channel protective film are successively formed. With the use of a resist mask formed by performing light exposure with the use of a photomask which is a multi-tone mask and development, i) in a region without the resist mask, the second insulating film, the semiconductor film, the first insulating film, and the conductive film are successively etched, ii) the resist mask is made to recede by ashing or the like and only the region of the resist mask with small thickness is removed, so that part of the second insulating film is exposed, and iii) the exposed part of the second insulating film is etched, so that a pair of opening portions is formed.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: June 11, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuta Endo, Kosei Noda
  • Patent number: 8455913
    Abstract: LED epitaxial layers (n-type, p-type, and active layers) are grown on a substrate. For each die, the n and p layers are electrically bonded to a package substrate that extends beyond the boundaries of the LED die such that the LED layers are between the package substrate and the growth substrate. The package substrate provides electrical contacts and conductors leading to solderable package connections. The growth substrate is then removed. Because the delicate LED layers were bonded to the package substrate while attached to the growth substrate, no intermediate support substrate for the LED layers is needed. The relatively thick LED epitaxial layer that was adjacent the removed growth substrate is then thinned and its top surface processed to incorporate light extraction features.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: June 4, 2013
    Assignee: Phiips Lumileds Lighting Company LLC
    Inventors: John Epler, Paul S. Martin, Michael R. Krames