Patents Examined by Scott R. Wilson
  • Patent number: 9076902
    Abstract: An integrated optical receiver architecture may be used to couple light between a multi-mode fiber (MMF) and silicon chip which includes integration of a silicon de-multiplexer and a high-speed Ge photo-detector. The proposed architecture may be used for both parallel and wavelength division multiplexing (WDM) based optical links with a data rate of 25 Gb/s and beyond.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: July 7, 2015
    Assignee: Intel Corporation
    Inventor: Ansheng Liu
  • Patent number: 9048203
    Abstract: A light emitting device having high definition, a high aperture ratio, and high reliability is provided. The present invention achieves high definition and a high aperture ratio with a full color flat panel display using red, green, and blue color emission light by intentionally forming laminate portions, wherein portions of different organic compound layers of adjacent light emitting elements overlap with each other, without depending upon the method of forming the organic compound layers or the film formation precision.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: June 2, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toshiji Hamatani, Toru Takayama
  • Patent number: 9040369
    Abstract: The present disclosure provides a method for forming a semiconductor device that includes forming a replacement gate structure overlying a channel region of a substrate. A mandrel dielectric layer is formed overlying source and drain regions of the substrate. The replacement gate structure is removed to provide an opening exposing the channel region of the substrate. A functional gate structure is formed over the channel region including a work function metal layer. A protective cap structure is formed over the functional gate structure. At least one via is etched through the mandrel dielectric layer selective to the protective cap structure to expose a portion of at least one of the source region and the drain region. A conductive fill is then formed in the vias to provide a contact to the at least one of the source region and the drain region.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: May 26, 2015
    Assignee: International Business Machines Corporation
    Inventors: Shahab Siddiqui, Michael P. Chudzik, Carl J. Radens
  • Patent number: 9041007
    Abstract: A MOSFET cell of a semiconductor device includes a polysilicon gate electrode and an n+-source region formed in an upper portion of an n?-drift layer. An interlayer insulating film covers the gate electrode. An Al source electrode extends on the interlayer insulating film. An Al gate pad is connected to the gate electrode. A barrier metal layer that prevents diffusion of aluminum is interposed between the source electrode and the interlayer insulating film, and between the gate pad and the gate electrode.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: May 26, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Eisuke Suekawa, Yasunori Oritsuki, Yoichiro Tarui
  • Patent number: 9041145
    Abstract: The performances of a semiconductor device are improved. Between a memory gate electrode and a p type well, and between a control gate electrode and the memory gate electrode of a split gate type nonvolatile memory, an insulation film having a charge accumulation layer therein is formed. The insulation film includes a lamination film of a silicon oxide film, a silicon nitride film formed thereover, another silicon oxide film formed thereover, and an insulation film formed thereover, and thinner than the upper silicon oxide film. The insulation film is in contact with the memory gate electrode including polysilicon. The insulation film is formed of a metal compound containing at least one of Hf, Zr, Al, Ta, and La, and hence can cause Fermi pinning, and has a high dielectric constant.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: May 26, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Yoshiyuki Kawashima
  • Patent number: 8999769
    Abstract: A method of forming a device is disclosed. A substrate defined with a device region is provided. A gate having an upper and a lower portion is formed in a trench in the substrate in the device region. The upper portion forms a gate electrode and the lower portion forms a gate field plate. First and second surface doped regions are formed adjacent to the gate. The gate field plate introduces vertical reduced surface (RESURF) effect in a drift region of the device.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: April 7, 2015
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Purakh Raj Verma, Liang Yi, Yemin Dong
  • Patent number: 8952360
    Abstract: An organic light-emitting display apparatus includes a substrate, a first electrode on the substrate; an intermediate layer on the first electrode, the intermediate layer including an organic light-emitting layer; a second electrode on the intermediate layer, a first inorganic encapsulating layer on the second electrode, the first inorganic encapsulating layer defining a first groove formed therein; a first organic encapsulating layer that is in the first groove defined by the first inorganic encapsulating layer, the first organic encapsulating layer not extending beyond the first groove, and a second inorganic encapsulating layer on the first organic encapsulating layer.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: February 10, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sang-Hun Oh, Gyoo-Chul Jo
  • Patent number: 8941096
    Abstract: By introducing new concepts into a structure of a conventional organic semiconductor element and without using a conventional ultra thin film, an organic semiconductor element is provided which is more reliable and has higher yield. Further, efficiency is improved particularly in a photoelectronic device using an organic semiconductor. Between an anode and a cathode, there is provided an organic structure including alternately laminated organic thin film layer (functional organic thin film layer) realizing various functions by making an SCLC flow, and a conductive thin film layer (ohmic conductive thin film layer) imbued with a dark conductivity by doping it with an acceptor and a donor, or by the like method.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: January 27, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuo Tsutsui, Hiroko Yamazaki, Satoshi Seo
  • Patent number: 8933539
    Abstract: An integrated circuit (IC) and a seal ring thereof are provided. The IC includes a first seal ring. The first seal ring is disposed in the IC. The first seal ring includes at least one stagger structure. The at least one stagger structure includes at least one stagger unit. The at least one stagger unit makes staggered connection with another neighboring stagger unit.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: January 13, 2015
    Assignee: VIA Telecom Co., Ltd.
    Inventors: Bing-Jye Kuo, Hong-Wen Lin, Yu-Jie Ji
  • Patent number: 8933467
    Abstract: A light emitting diode (LED) system includes a substrate, an application specific integrated circuit (ASIC), and at least one light emitting diode (LED) that includes a Group-III nitride based material such as GaN, InGaN, AlGaN, AlInGaN or other (Ga, In or Al) N-based materials. The light emitting diode (LED) system can also include a polymer lens, and a phosphor layer on the lens or light emitting diode (LED) for producing white light. In addition, multiple light emitting diodes (LEDs) can be mounted on the substrate, and can have different colors for smart color control lighting. The substrate and the application specific integrated circuit (ASIC) are configured to provide an integrated LED circuit having smart functionality. In addition, the substrate is configured to compliment and expand the functions of the application specific integrated circuit (ASIC), and can also include built in integrated circuits for performing additional electrical functions.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: January 13, 2015
    Assignee: SemiLEDS Optoelectronics Co., Ltd.
    Inventors: Trung Tri Doan, Tien Wei Tan, Wen-Huang Liu, Chen-Fu Chu, Yung Wei Chen
  • Patent number: 8928007
    Abstract: An electro-optical device includes: a pixel region that is formed on a substrate and in which a light emitting element that has a first electrode, a second electrode and a light emitting layer formed between the first electrode and the second electrode is arranged; a partition wall portion that is formed above the substrate and located on an outer side of the pixel region; a connecting line that is formed above the substrate and located on an outer side of the partition wall portion; and a connecting section that is formed above the substrate and electrically connects the second electrode to the connecting line, wherein the second electrode covers and extends over the pixel region and the partition wall portion and does not overlap the connecting line in a planar view.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: January 6, 2015
    Assignee: Seiko Epson Corporation
    Inventors: Suguru Akagawa, Yuki Hanamura
  • Patent number: 8890272
    Abstract: A photodetector is provided, comprising: a radiation-absorbing semiconductor region and a collection semiconductor region separated by and each in contact with a barrier semiconductor region; wherein, at least in the absence of an applied bias voltage, the band gap between the valence band energy and the conduction band energy of the barrier semiconductor region is offset from the band gap between the valence band energy and the conduction band energy of the radiation-absorbing semiconductor region so as to form an energy barrier between the radiation-absorbing semiconductor region and the collection semiconductor region which resists the flow of minority carriers from the radiation-absorbing semiconductor region to the collection semiconductor region. Also provided is a method of manufacturing a photodetector.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: November 18, 2014
    Assignee: BAH Holdings LLC
    Inventor: Michael Tkachuk
  • Patent number: 8878226
    Abstract: A light emitting device includes a substrate, and a plurality of light emitting structures disposed thereon. Each of the light emitting structures includes an auxiliary electrode disposed on the substrate, a first insulating layer disposed on the substrate and covering the auxiliary electrode, an electrode disposed on the first insulating layer, a second insulating layer disposed on the first insulating layer and having a first opening exposing the electrode, an organic light emitting layer disposed in the first opening, a cathode disposed on the organic light emitting layer, at least a conductive structure penetrating through the first insulating layer and the second insulating layer, and a closed ring structure disposed on the second insulating layer and around the cathode, wherein a thickness of the closed ring structure is larger than that of the cathode.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: November 4, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Jing-Yi Yan, Shu-Tang Yeh, Chih-Chieh Hsu, Chen-Wei Lin, Kuang-Jung Chen
  • Patent number: 8853802
    Abstract: A method that includes forming a first layer having a first dopant concentration, the first layer having an integrated circuit region and a micro-electromechanical region and doping the micro-electromechanical region of the first layer to have a second dopant concentration is presented. The method includes forming a second layer having a third dopant concentration overlying the first layer, doping the second layer that overlies the micro-electromechanical region to have a fourth dopant concentration, forming a micro-electromechanical structure in the micro-electromechanical region using the first and second layers, and forming active components in the integrated circuit region using the second layer.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: October 7, 2014
    Assignees: STMicroelectronics, Inc., STMicroelectronics Asia Pacific PTE, Ltd.
    Inventors: Venkatesh Mohanakrishnaswamy, Olivier Le Neel, Loi N. Nguyen
  • Patent number: 8853700
    Abstract: Cross-coupling between a gate conductor and an active region of a semiconductor substrate is provided by forming a gate dielectric layer on the semiconductor substrate and lithographically patterning the gate dielectric layer to form opening therein over a portion of the active region at which electrical contact with the gate conductor is desired. After implanting electrical dopants, a gate conductor layer is deposited and patterned. A remaining portion of the gate conductor layer includes an integral conductor structure, which includes a first portion overlying a gate dielectric over an active region and a second portion contacting the semiconductor material of the same active region or a different active region. The gate dielectric layer can be deposited within gate cavities in planarization dielectric material layer in a replacement gate scheme, or can be deposited on planar surfaces of active regions and/or shallow trench isolation structures in a gate first processing scheme.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: October 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Viraj Y. Sardesai, Robert C. Wong
  • Patent number: 8823162
    Abstract: An integrated circuit die stack including a first integrated circuit die mounted upon a substrate, the first die including pass-through vias (‘PTVs’) composed of conductive pathways through the first die with no connection to any circuitry on the first die; and a second integrated circuit die, identical to the first die, shifted in position with respect to the first die and mounted upon the first die, with the PTVs in the first die connecting signal lines from the substrate through the first die to through silicon vias (‘TSVs’) in the second die composed of conductive pathways through the second die connected to electronic circuitry on the second die; with the TSVs and PTVs disposed upon each identical die so that the positions of the TSVs and PTVs on each identical die are translationally compatible with respect to the TSVs and PTVs on the other identical die.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: September 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jimmy G. Foster, Sr., Kyu-Hyoun Kim
  • Patent number: 8816320
    Abstract: A GaN-containing semiconductor light emitting device includes: an n-type semiconductor layer formed of GaN-containing semiconductor, an active layer formed on the n-type semiconductor layer, formed of GaN-containing semiconductor, and having a multiple quantum well structure including a plurality of barrier layers and well layers stacked alternately, and a p-type semiconductor layer formed on the active layer and formed of GaN-containing semiconductor, wherein: the barrier layers comprise: a first barrier layer disposed nearest to the n-type semiconductor layer among the barrier layers and formed of a GaN/AlGaN layer, and second barrier layers disposed nearer to the p-type semiconductor layer than the first barrier layer and including an InGaN/GaN layer which has a layered structure of a InGaN sublayer and a GaN sublayer; and the well layers are each formed of an InGaN layer having a narrower band gap than that in the InGaN sublayer.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: August 26, 2014
    Assignee: Stanley Electric Co., Ltd.
    Inventors: Sho Iwayama, Masahiko Moteki
  • Patent number: 8766323
    Abstract: An organic light emitting display apparatus and method of manufacturing the organic light emitting display apparatus including a lower substrate having power lines in a non-display region that is outside a display region whereon an image is realized; and a functional layer formed between the power lines and an encapsulation substrate.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: July 1, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Eun-Ah Kim, Tae-Kyu Kim, Young-Hee An, Jae-Yong Kim
  • Patent number: 8729678
    Abstract: An image sensor includes first pixels, second pixels and a deep trench. The first pixels are formed in an active region of a semiconductor substrate, and configured to measure photo-charges corresponding to incident light. The second pixels are formed in an optical-black region of the semiconductor substrate, and are configured to measure black levels. The deep trench is formed vertically in a boundary region of the optical-black region, where the boundary region is adjacent to the active region, and configured to block leakage light and diffusion carriers from the active region.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: May 20, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-Sub Shim, Jung-Chak Ahn, Moo-Sup Lim, Hyung-Jin Bae, Min-Seok Oh
  • Patent number: 8716630
    Abstract: A visually seamless method of joining a first piece of metal and a second piece of metal is described. The first piece of metal is placed in contact with an edge of the second piece of metal. In some embodiments, the edge includes a sacrificial lip. The first piece of metal forming a junction area with the edge of the second piece of metal, applying a forging force to the first piece of metal, the forging force having an effect of creating an extremely tight fit up between the first and the second pieces of metal, welding the first and the second pieces to form an assembly and forming a cosmetically enhancing protective layer on the surface of the assembly, the protective layer obscuring any visible artifacts on the surface of the assembly, the obscured visible artifacts including any discoloration or discontinuity created by the laser welding.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: May 6, 2014
    Assignee: Apple Inc.
    Inventors: Carlo Catalano, Derrick Jue, Brian Miehm, Takahiro Oshima, Masashige Tatebe