Abstract: A voltage converter includes an output circuit having a high-side device and a low-side device which can be formed on a single die (a “PowerDie”). The high-side device can include a lateral diffused metal oxide semiconductor (LDMOS) while the low-side device can include a trench-gate vertical diffused metal oxide semiconductor (VDMOS). The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with the output circuit.

Abstract: A method of forming a vertical III-nitride based light emitting diode structure and a vertical III-nitride based light emitting diode structure can be provided. The method comprises forming a III-nitride based light emitting structure on a silicon-on-insulator (SOI) substrate; forming a metal-based electrode structure on the III-nitride based light emitting structure; and removing the SOI substrate by a layer transfer process such that the metal-based electrode structure functions as a metal-based substrate of the light emitting structure.

Abstract: Super-junction MOSFETs by trench fill system requires void-free filling epitaxial growth. This may require alignment of plane orientations of trenches in a given direction. Particularly, when column layout at chip corner part is bilaterally asymmetrical with a diagonal line between chip corners, equipotential lines in a blocking state are curved at corner parts due to column asymmetry at chip corner. This tends to cause points where equipotential lines become dense, which may cause breakdown voltage reduction. In the present invention, in power type semiconductor active elements such as power MOSFETs, a ring-shaped field plate is disposed in chip peripheral regions around an active cell region, etc., assuming a nearly rectangular shape. The field plate has an ohmic-contact part in at least a part of the portion along the side of the rectangle. However, in the portion corresponding to the corner part of the rectangle, an ohmic-contact part is not disposed.

Abstract: The disclosure relates to a stacked type power device module. May use the vertical conductive layer for coupling the stacked devices, the electrical transmission path may be shortened. Hence, current crowding or contact damages by employing the conductive vias or wire bonding may be alleviated.

Abstract: Provided is a structure of a transistor, which enables a so-called normally-off switching element, and a manufacturing method thereof. Provided is a structure of a semiconductor device which achieves high-speed response and high-speed operation by improving on characteristics of a transistor, and a manufacturing method thereof. Provided is a highly reliable semiconductor device. In the transistor in which a semiconductor layer, source and drain electrode layers, a gate insulating layer, and a gate electrode layer are stacked in that order. As the semiconductor layer, an oxide semiconductor layer which contains at least four kinds of elements of indium, gallium, zinc, and oxygen, and has a composition ratio (atomic percentage) of indium as twice or more as a composition ratio of gallium and a composition ratio of zinc, is used.

Abstract: An object is to provide a method for manufacturing a highly reliable semiconductor device which includes a thin film transistor using an oxide semiconductor and having stable electric characteristics. In manufacture of a semiconductor device in which an oxide semiconductor is used for a channel formation region, after an oxide semiconductor film is formed, a conductive film including a metal, a metal compound, or an alloy that can absorb or adsorb moisture, a hydroxy group, or hydrogen is formed to overlap with the oxide semiconductor film with an insulating film provided therebetween. Then, heat treatment is performed in the state where the conductive film is exposed; in such a manner, activation treatment for removing moisture, oxygen, hydrogen, or the like adsorbed onto a surface of or in the conductive film is performed.

Abstract: Disclosed herein is a thin film transistor. The thin film transistor is characterized in having a source interconnect layer and a drain interconnect layer. The source electrode and the drain electrode are respectively disposed above and in contact with the source interconnect layer and the drain interconnect layer. The semiconductor layer is in contact with both the source interconnect layer and the drain interconnect layer, but is not in contact with the source electrode and the drain electrode.

Abstract: A method for forming a semiconductor structure having a transistor device with a control electrode for controlling a flow of carriers between a first electrode and a second electrode. A passivation layer is deposited over the first electrode, the second electrode and the control electrode. An etch stop layer is deposited on the passivation layer over the control electrode. A dielectric layer is formed over the etch stop layer. A window is etched through a selected region in the dielectric layer over the control electrode, to expose a portion of the etch stop layer disposed over the control electrode. A metal layer is formed on a portion of the etch stop layer and the dielectric layer is also formed on the metal layer. A second metal layer is deposited on the portion of the dielectric layer formed on the first mentioned metal layer.

Abstract: An integrated optical receiver architecture may be used to couple light between a multi-mode fiber (MMF) and silicon chip which includes integration of a silicon de-multiplexer and a high-speed Ge photo-detector. The proposed architecture may be used for both parallel and wavelength division multiplexing (WDM) based optical links with a data rate of 25 Gb/s and beyond.

Abstract: A light emitting device having high definition, a high aperture ratio, and high reliability is provided. The present invention achieves high definition and a high aperture ratio with a full color flat panel display using red, green, and blue color emission light by intentionally forming laminate portions, wherein portions of different organic compound layers of adjacent light emitting elements overlap with each other, without depending upon the method of forming the organic compound layers or the film formation precision.

Abstract: The performances of a semiconductor device are improved. Between a memory gate electrode and a p type well, and between a control gate electrode and the memory gate electrode of a split gate type nonvolatile memory, an insulation film having a charge accumulation layer therein is formed. The insulation film includes a lamination film of a silicon oxide film, a silicon nitride film formed thereover, another silicon oxide film formed thereover, and an insulation film formed thereover, and thinner than the upper silicon oxide film. The insulation film is in contact with the memory gate electrode including polysilicon. The insulation film is formed of a metal compound containing at least one of Hf, Zr, Al, Ta, and La, and hence can cause Fermi pinning, and has a high dielectric constant.

Abstract: A MOSFET cell of a semiconductor device includes a polysilicon gate electrode and an n+-source region formed in an upper portion of an n?-drift layer. An interlayer insulating film covers the gate electrode. An Al source electrode extends on the interlayer insulating film. An Al gate pad is connected to the gate electrode. A barrier metal layer that prevents diffusion of aluminum is interposed between the source electrode and the interlayer insulating film, and between the gate pad and the gate electrode.

Abstract: The present disclosure provides a method for forming a semiconductor device that includes forming a replacement gate structure overlying a channel region of a substrate. A mandrel dielectric layer is formed overlying source and drain regions of the substrate. The replacement gate structure is removed to provide an opening exposing the channel region of the substrate. A functional gate structure is formed over the channel region including a work function metal layer. A protective cap structure is formed over the functional gate structure. At least one via is etched through the mandrel dielectric layer selective to the protective cap structure to expose a portion of at least one of the source region and the drain region. A conductive fill is then formed in the vias to provide a contact to the at least one of the source region and the drain region.

Abstract: A method of forming a device is disclosed. A substrate defined with a device region is provided. A gate having an upper and a lower portion is formed in a trench in the substrate in the device region. The upper portion forms a gate electrode and the lower portion forms a gate field plate. First and second surface doped regions are formed adjacent to the gate. The gate field plate introduces vertical reduced surface (RESURF) effect in a drift region of the device.

Abstract: An organic light-emitting display apparatus includes a substrate, a first electrode on the substrate; an intermediate layer on the first electrode, the intermediate layer including an organic light-emitting layer; a second electrode on the intermediate layer, a first inorganic encapsulating layer on the second electrode, the first inorganic encapsulating layer defining a first groove formed therein; a first organic encapsulating layer that is in the first groove defined by the first inorganic encapsulating layer, the first organic encapsulating layer not extending beyond the first groove, and a second inorganic encapsulating layer on the first organic encapsulating layer.

Abstract: By introducing new concepts into a structure of a conventional organic semiconductor element and without using a conventional ultra thin film, an organic semiconductor element is provided which is more reliable and has higher yield. Further, efficiency is improved particularly in a photoelectronic device using an organic semiconductor. Between an anode and a cathode, there is provided an organic structure including alternately laminated organic thin film layer (functional organic thin film layer) realizing various functions by making an SCLC flow, and a conductive thin film layer (ohmic conductive thin film layer) imbued with a dark conductivity by doping it with an acceptor and a donor, or by the like method.

Abstract: A light emitting diode (LED) system includes a substrate, an application specific integrated circuit (ASIC), and at least one light emitting diode (LED) that includes a Group-III nitride based material such as GaN, InGaN, AlGaN, AlInGaN or other (Ga, In or Al) N-based materials. The light emitting diode (LED) system can also include a polymer lens, and a phosphor layer on the lens or light emitting diode (LED) for producing white light. In addition, multiple light emitting diodes (LEDs) can be mounted on the substrate, and can have different colors for smart color control lighting. The substrate and the application specific integrated circuit (ASIC) are configured to provide an integrated LED circuit having smart functionality. In addition, the substrate is configured to compliment and expand the functions of the application specific integrated circuit (ASIC), and can also include built in integrated circuits for performing additional electrical functions.

Abstract: An integrated circuit (IC) and a seal ring thereof are provided. The IC includes a first seal ring. The first seal ring is disposed in the IC. The first seal ring includes at least one stagger structure. The at least one stagger structure includes at least one stagger unit. The at least one stagger unit makes staggered connection with another neighboring stagger unit.

Abstract: An electro-optical device includes: a pixel region that is formed on a substrate and in which a light emitting element that has a first electrode, a second electrode and a light emitting layer formed between the first electrode and the second electrode is arranged; a partition wall portion that is formed above the substrate and located on an outer side of the pixel region; a connecting line that is formed above the substrate and located on an outer side of the partition wall portion; and a connecting section that is formed above the substrate and electrically connects the second electrode to the connecting line, wherein the second electrode covers and extends over the pixel region and the partition wall portion and does not overlap the connecting line in a planar view.

Abstract: A photodetector is provided, comprising: a radiation-absorbing semiconductor region and a collection semiconductor region separated by and each in contact with a barrier semiconductor region; wherein, at least in the absence of an applied bias voltage, the band gap between the valence band energy and the conduction band energy of the barrier semiconductor region is offset from the band gap between the valence band energy and the conduction band energy of the radiation-absorbing semiconductor region so as to form an energy barrier between the radiation-absorbing semiconductor region and the collection semiconductor region which resists the flow of minority carriers from the radiation-absorbing semiconductor region to the collection semiconductor region. Also provided is a method of manufacturing a photodetector.