Abstract: Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area.

Abstract: A semiconductor structure includes a substrate, a gate structure disposed over the substrate, a dielectric material disposed over the substrate and the gate structure, a conductive structure extending within the dielectric material, and a void extending within the dielectric material and disposed over the gate structure.

Abstract: Integrated circuit layouts are disclosed that include metal layers with metal tracks having separate metal sections along the metal tracks. The separate metal sections along a single track may be electrically isolated from each other. The separate metal sections may then be electrically connected to different voltage tracks in metal layers above and/or below the metal layer with the separate metal sections. One or more of the metal layers in the integrated circuit layouts may also include metal tracks at different voltages (e.g., power and ground) that are adjacent to each other within a power grid layout. The metal tracks may be separated by electrically insulating material. The metal tracks and the electrically insulating material between the tracks may create capacitance in the power grid layout.

Abstract: A semiconductor device is provided, which includes providing an active region, a source region, a drain region, a dielectric layer, a gate structure and a nitrogen-infused dielectric layer. The source region and the drain region are formed in the active region. The dielectric layer is disposed over the source region and the drain region. The gate structure formed in the dielectric layer is positioned between the source region and the drain region. The nitrogen-infused dielectric layer is disposed over the dielectric layer and over the gate structure.

Abstract: Provided is a semiconductor device. The device comprises an epitaxial layer that constitutes a part of an active cell region and is doped with impurities of a first conductivity type at a first concentration; a field stop region that is located below the epitaxial layer and doped with impurities of a second conductivity type at a second concentration which are then activated; and a collector region that is located below the field stop region 70 and is doped with impurities of a second conductivity type. The field stop region is formed by repeatedly alternately arranging regions in which the activation of the impurities of the first conductivity type is relatively strong and regions in which the activation of the impurities of the first conductivity type is relatively weak.

Abstract: A method includes encapsulating structures disposed on or over a surface of a substrate in an encapsulant. The method also includes separating the encapsulant from the substrate. An apparatus includes a composite film having structures embedded in an encapsulant. The composite film has a surface with a surface roughness of less than one nm. An apparatus includes an encapsulant film having a surface with indentations formed therein. The surface has a surface roughness apart from the indentations of less than one nm.

Abstract: Embodiments relate to forming an elastomeric interface layer (elayer) with a flap over multiple light emitting diode (LED) dies by forming materials across multiple LED dies and removing the materials between the LED dies. The formed flap of the elayer provides a large surface area for adhesion between each LED and a pick-up surface. For example, the flap may have a surface area that is larger than the light emitting surface of the LED die, or larger than the surface area of an elastomeric interface layer without the flap. As such, the elayer allows each LED to be picked up by a pick-up surface and placed onto a display substrate including control circuits for sub-pixels of an electronic display. In some embodiments, the LED dies are micro-LED (?LED) dies.

Abstract: A semiconductor device includes a channel structure, a dielectric structure, a gate structure, a first conductive structure, and a second conductive structure. The channel structure has a top surface, a bottom surface, and a sidewall extending from the top surface to the bottom surface. The first conductive structure is disposed on the bottom surface of the channel structure and includes a body portion and at least one convex portion, and a top surface of the convex portion is higher than a top surface of the body portion. The second conductive structure is disposed on the top surface of the channel structure and includes a body portion and at least one convex portion, and a bottom surface of the body portion is higher than a bottom surface of the convex portion.

Abstract: Electrostatic discharge (ESD) protection device is provided. An ESD device includes a substrate having an input region; a plurality of fins on the substrate in the input region; a well region, doped with first-type ions, in the plurality of fins and in the substrate; an epitaxial layer on each fin in the input region; a drain region, doped with second-type ions, in a top portion of each fin and in the epitaxial layer; an extended drain region, doped with the second-type ions, in a bottom portion of each fin to connect to the drain region and in a portion of the substrate, in the input region; and a counter-doped region, doped with the first-type ions, in a portion of the substrate between two adjacent fins to insulate adjacent extended drain regions.

Abstract: A radiation emitting device comprising light scattering particles of different sizes that at least partially surround an emitter, improving the spatial color mixing and color uniformity of the device. Multiple sizes of light scattering particles are dispersed in a medium to at least partially surround a single- or multiple-chip polychromatic emitter package. The different sizes of light scattering particles interact with corresponding wavelength ranges of emitted radiation. Thus, radiation emitted over multiple wavelength ranges or sub-ranges can be efficiently scattered to eliminate (or intentionally create) spatially non-uniform color patterns in the output beam.

Abstract: A light-emitting device includes: a light-emitting element; a coating member that covers the light-emitting element; and two external connection electrodes exposed form a first surface of the coating member. Each of the external connection electrodes includes an electrode buried in the coating member; and a metal layer formed on the electrode. A surface of each of the metal layers is exposed from the first surface of the coating member. The first surface of the coating member includes a plurality of grooves between the external connection electrodes.

Abstract: A semiconductor device includes first and second Fin FETs and a separation plug made of an insulating material and disposed between the first and second Fin FETs. The first Fin FET includes a first fin structure extending in a first direction, a first gate dielectric formed over the first fin structure and a first gate electrode formed over the first gate dielectric and extending in a second direction perpendicular to the first direction. The second Fin FET includes a second fin structure, a second gate dielectric formed over the second fin structure and a second gate electrode formed over the first gate dielectric and extending in the second direction. When viewed from above, an end shape the separation plug has a concave curved shape, while an end of the first gate electrode abutting the separation plug has a convex curved shape.

Abstract: An approach to creating a semiconductor chip including a semiconductor substrate with one or more topside metal layers and one or more backside metal layers. The approach creates the semiconductor chip with one or more semiconductor devices with wiring interconnects in the one or more topside metal layers on the semiconductor substrate and one or more inductors in the one or more backside metal layer. Furthermore, the approach creates the semiconductor chip with one or more through silicon vias extending through the semiconductor substrate connecting the one or more inductors in the one or more backside metal layers and the one or more semiconductor devices with wiring interconnects in the one or more topside metal layers on the semiconductor substrate.

Abstract: In an embodiment, a method includes: forming a first fin extending from a substrate, the substrate including silicon, the first fin including silicon germanium; forming an isolation region around the first fin, an oxide layer being formed on the first fin during formation of the isolation region; removing the oxide layer from the first fin with a hydrogen-based etching process, silicon at a surface of the first fin being terminated with hydrogen after the hydrogen-based etching process; desorbing the hydrogen from the silicon at the surface of the first fin to depassivate the silicon; and exchanging the depassivated silicon at the surface of the first fin with germanium at a subsurface of the first fin.

Abstract: A semiconductor package includes a first die having a first substrate, an interconnect structure overlying the first substrate and having multiple metal layers with vias connecting the multiple metal layers, a seal ring structure overlying the first substrate and along a periphery of the first substrate, the seal ring structure having multiple metal layers with vias connecting the multiple metal layers, the seal ring structure having a topmost metal layer, the topmost metal layer being the metal layer of the seal ring structure that is furthest from the first substrate, the topmost metal layer of the seal ring structure having an inner metal structure and an outer metal structure, and a polymer layer over the seal ring structure, the polymer layer having an outermost edge that is over and aligned with a top surface of the outer metal structure of the seal ring structure.

Abstract: An organic light emitting display apparatus includes a first electrode on a substrate and a plurality of organic layers on the first electrode and including a first region and a second region. The organic light emitting display apparatus further includes a second electrode on the plurality of organic layers. A thickness of the plurality of organic layers in the first region can be different from a thickness of the plurality of organic layers in the second region.

Abstract: A semiconductor device is provided. The semiconductor device includes: a first wire pattern disposed on a substrate and extending in a first direction; a first gate electrode surrounding the first wire pattern and extending in a second direction, the first direction intersecting the second direction perpendicularly; a first transistor including the first wire pattern and the first gate electrode; a second wire pattern disposed on the substrate and extending in the first direction; a second gate electrode surrounding the second wire pattern and extending in the second direction; and a second transistor including the second wire pattern and the second gate electrode, wherein a width of the first wire pattern in the second direction is different from a width of the second wire pattern in the second direction.

Abstract: The present disclosure discloses a thin film transistor array substrate, a display panel and a display device. The array substrate includes a substrate and an electrostatic discharge circuit layer, and the electrostatic discharge circuit layer is disposed in the non-display area at a side of the substrate and includes a conductive circuit disposed around the display area and electrostatic discharge devices electrically connected with the conductive circuit. The electrostatic discharge device includes a plurality of electrostatic discharge units disposed at intervals, one end of each of the electrostatic discharge units is connected with an edge of the substrate and the other end thereof is connected with the conductive circuit.

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and first fuse branches and second fuse branches are formed in the substrate, in which the first fuse branches and the second fuse branches are separated by a shallow trench isolation (STI) and the second fuse branches include different sizes. Next, fuse elements are formed to connect the first fuse branches and the second fuse branches.

Abstract: Provided is a Schottky barrier diode which is configured from a Ga2O3-based semiconductor, and has a lower rising voltage than a conventional one. In one embodiment, the Schottky barrier diode 1 is provided which has: a semiconductor layer 10 configured from a Ga2O3-based single crystal; an anode electrode 11 which forms a Schottky junction with the semiconductor layer 10, and has a portion which contacts the semiconductor layer 10 and is composed of Fe or Cu; and a cathode electrode 12.