Abstract: A method of fabricating a semiconductor structure having multiple semiconductor device layers is provided. The method comprises providing a bulk substrate and growing a first channel material on the bulk substrate wherein the lattice constant of the first channel material is different from the lattice constant of the bulk substrate to introduce strain to the first channel material. The method further comprises fabricating a first semiconductor device layer on the bulk substrate with the strained first channel material, fabricating a buffer layer comprising dielectric material with a blanket top surface above the first semiconductor layer, bonding to the blanket top surface a bottom surface of a second substrate comprising a buried oxide with a second channel material above the buried oxide, and fabricating a second semiconductor device layer on the second substrate.

Abstract: A semiconductor device is provided. The semiconductor device includes a gate spacer that defines a trench on a substrate and includes an upper part and a lower part, a gate insulating film that extends along sidewalls and a bottom surface of the trench and is not in contact with the upper part of the gate spacer, a lower conductive film that extends on the gate insulating film along the sidewalls and the bottom surface of the trench and is not overlapped with the upper part of the gate spacer, and an upper conductive film on an uppermost part of the gate insulating film on the lower conductive film.

Abstract: A microfluidic chip suitable for detecting a microdroplet includes a first component, a second component, a channel layer, and a semiconductor chip. The first component includes a first substrate, a first electrode layer, and a first dielectric layer, wherein the first electrode layer is located between the first substrate and the first dielectric layer. The second component is disposed opposite to the first component and includes a second substrate, a second electrode layer, and a second dielectric layer. The channel layer is located between the first component and the second component. The semiconductor chip is disposed at one side of the first substrate and is exposed to the channel layer to assist in treating or detecting a sample or microdroplet. The microdroplet in the sample entering the channel layer is reacted with the semiconductor chip, and thus the sample is detected.

Abstract: A manufacturing method of an LED package structure includes the steps as follows: providing an LED package structure assembly, which has a substrate layer, an LED chip set located on the substrate layer, and an encapsulating gel layer covering the LED chip set; taking a first blade to saw the LED package structure assembly from the encapsulating gel layer to the substrate layer until a plurality of sawing grooves are formed on the substrate layer; and taking a second blade to saw the LED package structure assembly along each sawing groove until the second blade passes through the substrate layer, thereby forming a plurality of LED package structures separated from each other. Wherein a hardness of the first blade is greater than that of the second blade, and a thickness of the second blade is less than that of the first blade.

Abstract: A semiconductor substrate having a through-silicon via with an air gap interposed between the through-silicon via and the semiconductor substrate is provided. An opening is formed partially through the semiconductor substrate. The opening is first lined with a first liner and then the opening is filled with a conductive material. A backside of the semiconductor substrate is thinned to expose the first liner, which is subsequently removed and a second liner formed with a low-k or extra low-k dielectric is formed in its place.

Abstract: A method for manufacturing a flash memory device on a substrate may include: preparing the substrate with shallow trench isolation to define active sections; depositing a floating gate oxide layer on the prepared substrate; depositing a floating gate polysilicon layer on the floating gate oxide layer; polishing the floating gate polysilicon layer to isolate a plurality of floating gates above the active sections of the substrate; depositing a silicon nitride layer on top of the plurality of floating gates; patterning and etching the silicon nitride layer to create silicon nitride features; depositing a set of oxide spacers along sides of the silicon nitride features; implanting a source junction into the substrate beneath the individual floating gates; removing the floating gate polysilicon layer except where beneath individual oxide spacers, then removing the set of oxide spacers; depositing an inter-poly layer on top of the remaining floating gates; depositing a second polysilicon layer on top of the inter-

Abstract: A method to make light-emitting diode (LED) units include arranging LEDs in a pattern, forming an optically transparent spacer layer over the LEDs, forming an optically reflective layer over the LEDs, and singulating the LEDs into LED units. The method may further include, after forming the optically transparent spacer layer and before singulating the LEDs, forming a secondary light-emitting layer that conforms to the LEDs, cutting the LEDs to form LED groups having a same arrangement, spacing the LED groups on a support, and forming the optically reflective layer in spaces between the LED groups.

Abstract: A 3C—SiC buffer layer on Si(001) comprising a porous buffer layer of 3C—SiC on a Si(001) substrate, wherein the porous buffer layer is produced through a solid state reaction, and wherein an amorphous carbon layer on the Si(001) substrate is deposited by magnetron sputtering of a C target at room temperature at a rate of 0.8 nm/min.

Abstract: A light emitting device package can include first and second frames spaced apart from each other; a package body including a body portion between the first and second frames; a light emitting device including first and second electrode pads; first and second through holes in the first and second frames, respectively; a first resin between the body portion and the light emitting device; and a conductive material in the first and second through holes, in which the first and second electrode pads of the light emitting device respectively overlap with the first and second through holes, the first and second electrode pads are spaced apart from each other, and the conductive material in the first and second through holes respectively contacts the first and second electrode pads, and a first side surface of the first electrode pad and a second side surface of the second electrode pad facing the first side surface both contact the first resin.

Abstract: Techniques are disclosed for co-integrating transition metal dichalcogenide (TMDC)-based p-channel transistor devices and III-N semiconductor-based n-channel transistor devices. In accordance with some embodiments, a p-channel transistor device configured as described herein may include a layer of TMDC material such as, for example, tungsten diselenide, tungsten disulfide, molybdenum diselenide, or molybdenum disulfide, and an n-channel transistor device configured as described herein may include a layer of III-V material such as, for example, gallium nitride, aluminum nitride, aluminum gallium nitride, and indium aluminum nitride. Transistor structures provided as described herein may be utilized, for instance, in power delivery applications where III-N semiconductor-based n-channel power transistor devices can benefit from being integrated with low-leakage, high-performance p-channel devices providing logic and control circuitry.

Abstract: A device comprises a control gate structure and a memory gate structure over a substrate, a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer along a sidewall of the control gate structure, an oxide layer over a top surface of the memory gate structure, a top spacer over the oxide layer, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure.

Abstract: Disclosed is a thin film transistor, an array substrate, a method for manufacturing the same, and a display device. The method includes: forming a source and drain on a base substrate and forming a semiconductor layer. Between the step of forming the source and drain and the step of forming the semiconductor layer, the method further includes: forming a diffusion barrier layer. Metal atoms diffused from the source and drain and passing through the diffusion barrier layer react with a part of the semiconductor layer near the source and drain, and a metal transition layer containing metal silicide is formed.

Abstract: Described herein are methods and structures integrating one or more TMDC crystal heteroepitaxially grown on one or more group III-Nitride (III-N) crystal. The TMDC crystal may be grown on a III-N heteroepitaxial crystal that has been grown on crystalline silicon substrate. One or more of III-N devices and silicon devices employing separated regions of the heteroepitaxial substrate may be integrated with a TMDC device fabricated on with the TMDC crystal. In some embodiments, impurity-doped III-N source/drain regions provide a low resistance coupling between metallization and a TMDC-channeled transistor.

Abstract: A semiconductor device includes an active region over a substrate; a first cobalt-containing feature disposed over the active region; a conductive cap disposed over and in physical contact with the first cobalt-containing feature; and a second cobalt-containing feature disposed over and in physical contact with the conductive cap.

Abstract: A solid-state imaging device has a first substrate, a second substrate, and a third substrate. The first substrate has a plurality of first photoelectric conversion elements. The second substrate has a plurality of first through electrodes. The plurality of first photoelectric conversion elements are disposed in a pixel area. The plurality of first through electrodes are disposed only in a second area around a first area corresponding to the pixel area.

Abstract: A finFET structure includes an insulative cap over each gate in a vicinity of a first and second self-aligned contact (SAC) to source/drain regions thereof. The insulative cap has a bulbous upper insulative cap portion selectively grown to protect gate height loss during SAC opening formation. The bulbous upper insulative cap portion may be over just gates in the vicinity of the S/D regions, and optionally, over gates in the vicinity of a gate contact.

Abstract: To inhibit a decrease in inductance of an inductor in a plurality of semiconductor chips that are stacked. A semiconductor device includes: first and second semiconductor chips that are stacked; a first inductor; an arrangement-restricted region; and a circuit. In the semiconductor device, the first inductor is arranged in the first semiconductor chip. The arrangement-restricted region is provided in a region of the second semiconductor chip corresponding to the first inductor. The circuit is arranged in a region of the second semiconductor chip not corresponding to the arrangement-restricted region.

Abstract: Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area.

Abstract: The present invention provides a ceramic-aluminum bonded body in which Mg-containing oxide having a spinel crystal structure are dispersed in an aluminum member within a range of 2 ?m in a thickness direction from a bonded interface with a ceramic member, a segregated portion in which Mg, Si, and O is segregated is formed in the aluminum member in the vicinity of the bonded interface with the ceramic member, mass ratios of Mg, Si, and O between the segregated portion and a position spaced by 10 ?m from the bonded interface toward an aluminum member side are within predetermined ranges, and the amount of Mg at the position spaced by 10 ?m from the bonded interface toward the aluminum member side is 0.8 mass % or less.

Abstract: A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate of a first conductivity type, a first silicon carbide layer of the first conductivity type, and an insulating film. In the silicon carbide semiconductor device, no fluorine or chlorine is detectable in the insulating film, at a boundary layer of the insulating film and the first silicon carbide layer, or at the surface of first silicon carbide layer where the insulating film is provided.