Patents Examined by Scott Stowe
  • Making semiconductor devices by stacking strata of micro LEDS
    Patent number: 10600767
    Abstract: A stack of strata containing LEDs is fabricated by repeatedly bonding unpatterned epitaxial structures. Because the epitaxial structures are unpatterned (e.g., not patterned into individual micro LEDs), requirements on alignment are significantly relaxed. One example is an integrated multi-color LED display panel, in which arrays of micro LEDs are integrated with corresponding driver circuitry. Multiple strata of micro LEDs are stacked on top of a base substrate that includes the driver circuitry. In this process, each stratum is fabricated as follows. An unpatterned epitaxial structure is bonded on top of the existing device. The epitaxial structure is then patterned to form micro LEDs. The stratum is filled and planarized to allow the unpatterned epitaxial structure of the next stratum to be bonded. This is repeated to build up the stack of strata.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: March 24, 2020
    Assignee: Hong Kong Beida Jade Bird Display Limited
    Inventors: Wing Cheung Chong, Lei Zhang, Qiming Li, Jen-Shyan Chen
  • Compound semiconductor device and manufacturing method thereof
    Patent number: 10600901
    Abstract: A compound semiconductor device includes: a carrier transit layer; a carrier supply layer that is formed over the carrier transit layer and is made of InAlN; and a spacer layer that is formed between the carrier transit layer and the carrier supply layer and is made of at least one of AlGaN and InAlGaN.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: March 24, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Junji Kotani, Norikazu Nakamura, Tetsuro Ishiguro
  • Methods for patterning a magnetic sensing layer
    Patent number: 10593869
    Abstract: The present disclosure is directed towards a method for patterning a magnetic sensing layer. The method includes disposing a protective layer on a first of a substrate, disposing a first insulating layer on a first surface of protective layer. An opening is formed in the first insulating layer to expose the first surface of the protective layer. A magnetic sensing layer is disposed over the first insulating layer and a predetermined portion of the first surface of the protective layer within the opening. A second insulating layer can be disposed over the magnetic sensing layer. The second insulation layer and the magnetic sensing layer can be removed from the first insulation layer. Thus, the opening includes the magnetic sensing layer and the second insulation layer after the removal of the second insulation layer and magnetic sensing layer from the first insulation layer.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: March 17, 2020
    Assignee: Allegro MicroSystems, LLC
    Inventors: Harianto Wong, William P. Taylor
  • Transistors having ultra thin fin profiles and their methods of fabrication
    Patent number: 10593785
    Abstract: A transistor having an ultra thin fin profile and its method of fabrication is described. The transistor comprises a semiconductor substrate having an insulation layer formed on a semiconductor substrate. A fin extends from the semiconductor substrate. The fin has a subfin portion on the semiconductor substrate and an active fin portion on the subfin portion. The subfin portion is disposed in a trench formed in the insulation layer. The subfin portion comprises a III-V semiconductor material and the active fin portion comprises a group IV semiconductor material.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: March 17, 2020
    Assignee: Intel Corporation
    Inventors: Sanaz K. Gardner, Willy Rachmady, Van H. Le, Matthew V. Metz, Seiyon Kim, Ashish Agrawal, Jack T. Kavalieros
  • Ultraviolet light-emitting diode and electric apparatus provided with the same
    Patent number: 10593828
    Abstract: A UV LED element, which is an exemplary ultraviolet light-emitting diode according to the present invention, includes an n-type conductive layer, a light-emitting layer, an electron block layer, and a p-type contact layer, all of which are arranged in this order. Bandgap energy of the electron block layer satisfies Econtact?EEBL, where Econtact designates bandgap energy of the p-type contact layer and EEBL designates the bandgap energy of the electron block layer. The electric apparatus includes the UV LED element as a light source for emitting an ultraviolet ray.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: March 17, 2020
    Assignees: RIKEN, PANASONIC CORPORATION
    Inventors: Hideki Hirayama, Masafumi Jo, Takuya Mino, Norimichi Noguchi, Takayoshi Takano, Jun Sakai
  • Method for transferring graphene pieces onto a substrate
    Patent number: 10593762
    Abstract: Transferring graphene pieces onto a substrate, by the following steps: a) selecting a substrate comprising a plurality of placeholders for the graphene pieces; b) disposing and aligning the substrate on a substrate holder in a chamber; c) selecting a transfer layer having openings as placeholders for the graphene pieces; d) disposing and aligning the transfer layer on the substrate holder over the substrate so that the openings of the transfer layer are aligned over the placeholders on the substrate; e) adding liquid to the chamber to above the transfer layer, and raising the transfer layer on the liquid column; f) introducing graphene pieces onto the liquid film in the openings of the transfer layer; and g) reducing the distance between the substrate and the graphene pieces until the graphene pieces are disposed on the placeholders of the substrate. A substrate and a device for carrying out the method.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: March 17, 2020
    Assignee: Forschungszentrum Juelich GmbH
    Inventors: Dmitry Kireev, Dario Sarik, Bernhard Wolfrum, Andreas Offenhausser
  • Thin film transistor, array substrate, display panel and display device
    Patent number: 10586871
    Abstract: The present disclosure provides a thin film transistor, an array substrate, a display panel and a display device. The thin film transistor comprises a gate layer, a source and a drain located on the gate layer, and an active layer located on the source and the drain. The active layer is electrically connected to the source and the drain. The active layer comprises two sides arranged in parallel, and each side forms an acute angle of 45° with a face of the drain facing the source.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: March 10, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Zhenhua Lv, Zhiying Bao, Shijun Wang, Yong Zhang, Wenjun Xiao, Jingbo Xu
  • Thin film transistor and manufacturing method thereof
    Patent number: 10586874
    Abstract: The disclosure discloses a thin film transistor and a manufacturing method thereof. The method includes depositing quantum dot ink containing carbon quantum dots in a groove region between a source electrode and a drain electrode, after the quantum dot ink is dry, cleaning and blow-drying the dried quantum dot ink to film the carbon quantum dots to be an active layer of the thin film transistor. Accordingly, the disclosure can simplify the manufacturing process of the thin film transistor and enhance the production efficiency, as well as reducing costs and improving control sensitivity.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: March 10, 2020
    Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd
    Inventor: Huafei Xie
  • High-density metal-insulator-metal capacitors
    Patent number: 10580581
    Abstract: Methods for fabricating a structure that includes a metal-insulator-metal (MIM) capacitor and structures that include a MIM capacitor. The MIM capacitor includes a layer stack with a first electrode, a second electrode, and a third electrode. The layer stack includes a pilot opening extending at least partially through at least one of the first electrode, the second electrode, and the third electrode. A dielectric layer is arranged over the metal-insulator-metal capacitor, and includes a via opening extending vertically to the pilot opening. A via is arranged in the via opening and the pilot opening. The pilot opening has a cross-sectional area that is less than a cross-sectional area of the via opening.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: March 3, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Robert J. Fox, III, Lili Cheng, Roderick A. Augur
  • Display substrate, manufacturing method thereof, and display panel
    Patent number: 10581021
    Abstract: A display substrate, a manufacturing method thereof, and a display panel are disclosed. The display substrate includes a glass substrate; plural sub-pixels; and plural light extraction modules disposed on the glass substrate at plural regions in one-to-one correspondence with the plural sub-pixels; wherein each of the light extraction modules has a hemisphere-shaped groove structure. By manufacturing the plural light extraction modules each having a hemisphere structure and a higher refractive index on the glass substrate in one-to-one correspondence with the plural sub-pixels, the refraction angle of the light that is emitted from each of the sub-pixels and incident onto the glass substrate can be decreased, so that more light can be emitted out; in this way, it is possible to improve the luminous efficiency of the display substrate and hence the display effect of the display device.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: March 3, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Wei Zhang
  • Array substrate and manufacturing method thereof and display device
    Patent number: 10564496
    Abstract: The present application provides an array substrate, which is divided into a plurality of pixel units, wherein each pixel unit is provided therein with a light filtering structure, the light filtering structure includes a first light shielding part and a second light shielding part, the second light shielding part includes a second light shielding part body and a light transmitting hole penetrating through the second light shielding part body, a light transmitting gap exists between a inner boundary of an orthographic projection of the second light shielding part body on a layer in which the first light shielding part is provided and a boundary of the first light shielding part, a transparent light transmitting space is formed above the first light shielding part, and the light transmitting gap allows light with a predetermined wavelength to transmit therethrough.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: February 18, 2020
    Assignee: BOE Technology Group Co., Ltd.
    Inventor: Dongfang Wang
  • Semiconductor device and manufacturing method thereof
    Patent number: 10553690
    Abstract: A miniaturized transistor with reduced parasitic capacitance and highly stable electrical characteristics is provided. High performance and high reliability of a semiconductor device including the transistor is achieved. A first conductor is formed over a substrate, a first insulator is formed over the first conductor, a layer that retains fixed charges is formed over the first insulator, a second insulator is formed over the layer that retains fixed charges, and a transistor is formed over the second insulator. Threshold voltage Vth is controlled by appropriate adjustment of the thicknesses of the first insulator, the second insulator, and the layer that retains fixed charges.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: February 4, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuhiro Tanaka, Kazuki Tanemura, Daisuke Matsubayashi
  • System and method for substrate wafer back side and edge cross section seals
    Patent number: 10546750
    Abstract: Systems and methods for substrate wafer back side and edge cross section seals. In accordance with a first method embodiment, a silicon wafer of a first conductivity type is accessed. An epitaxial layer of the first conductivity type is grown on a front surface of the silicon wafer. The epitaxial layer is implanted to form a region of an opposite conductivity type. The growing and implanting are repeated to form a vertical column of the opposite conductivity type. The wafer may also be implanted to form a region of the opposite conductivity type vertically aligned with the vertical column.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: January 28, 2020
    Assignee: Vishay-Siliconix
    Inventors: Hamilton Lu, The-Tu Chau, Kyle Terrill, Deva N. Pattanayak, Sharon Shi, Kuo-In Chen, Robert Xu
  • Display substrate, method of fabricating the same, and display device
    Patent number: 10539836
    Abstract: A display substrate, a method of fabricating the same and a display device are provided. The display substrate includes a substrate and a groove formed on the substrate. The groove is formed by photoresist and the bottom surface of the groove exceeds a height of a pixel area.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: January 21, 2020
    Assignees: BOE Technology Group Co., Ltd., Hefei BOE Optoelectronics Technology Co., Ltd.
    Inventors: Guohua Xu, Ling Hu, Peng Zeng
  • Semiconductor device
    Patent number: 10529814
    Abstract: Machining accuracy of an IGBT region is worsened due to a height difference caused by polysilicon. Therefore, there is a problem that characteristic variation of the IGBT increases. Provided is a semiconductor device including a semiconductor substrate; a gate wiring layer provided on a front surface side of the semiconductor substrate; and a gate structure that includes a gate electrode and is provided on the front surface of the semiconductor substrate. The gate wiring layer includes an outer periphery portion that is a metal wiring layer and is provided along an outer periphery of the semiconductor substrate; and an extending portion that is a metal wiring layer, is provided extending from the outer periphery portion toward a central portion of the semiconductor substrate, and is electrically connected to the gate electrode.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: January 7, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuya Naito
  • Non-volatile memory device having nanocrystal floating gate and method of fabricating same
    Patent number: 10529729
    Abstract: Non-volatile memory devices and methods of fabricating thereof are disclosed herein. An exemplary non-volatile memory device includes a heterostructure disposed over a substrate. A gate structure traverses the heterostructure, such that the gate structure separates a source region and a drain region of the heterostructure and a channel region is defined between the source region and the drain region. The non-volatile memory device further includes a nanocrystal floating gate disposed in the channel region of the heterostructure between a first nanowire and a second nanowire. The first nanowire and the second nanowire extend between the source region and the drain region.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: January 7, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Jean-Pierre Colinge, Carlos H Diaz
  • Semiconductor device
    Patent number: 10529656
    Abstract: An object is to provide a semiconductor device having a plate electrode adapted to a plurality of chips, capable of being produced at low cost, and having high heat cycle property. A semiconductor device according to the present invention includes a plurality of semiconductor chips formed on a substrate, and a plate electrode connecting electrodes of the plurality of semiconductor chips. The plate electrode has half-cut portions formed by half-pressing and the raised sides of the half-cut portions are bonded with the electrodes of the semiconductor chips.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: January 7, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yoshihiro Yamaguchi, Yoshiko Obiraki
  • Lateral MOSFET with dielectric isolation trench
    Patent number: 10516045
    Abstract: A lateral trench MOSFET comprises an insulating layer buried in a substrate, a body region in the substrate, an isolation region in the substrate, a first drain/source region over the body region, a second drain/source region in the substrate, wherein the first drain/source region and the second drain/source region are on opposing sides of the isolation region, a drift region comprising a first drift region of a first doping density formed between the second drain/source region and the insulating layer, wherein the first drift region comprises an upper portion surrounded by isolation regions and a lower portion and a second drift region of a second doping density formed between the isolation region and the insulating layer, wherein a height of the second drift region is equal to a height of the lower portion of the first drift region.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Po-Yu Chen
  • Low on resistance high voltage metal oxide semiconductor transistor
    Patent number: 10510831
    Abstract: A high voltage transistor with low on resistance is disclosed. The transistor may include at least one cut out region in the drift region under the drain of the transistor. The cut out region is devoid of the drift well which connects the drain to the channel. Cut out regions may be distributed along the width direction of the drain region of the transistor. The transistor may alternatively or further include a vertical polysilicon plate surrounding the device region. The vertical polysilicon plate may be implemented as a deep trench isolation region. The deep trench isolation region includes a deep trench lined with an insulation collar and filled with polysilicon. The vertical polysilicon plate reduces an on resistance to improve device performance.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: December 17, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Namchil Mun, Jeoung Mo Koo, Shiang Yang Ong, Raj Verma Purakh
  • MRAM chip magnetic shielding
    Patent number: 10510946
    Abstract: Emerging memory chips and methods for forming an emerging memory chip are presented. For example, magnetic random access memory (MRAM) chip magnetic shielding and methods of forming a magnetic shield processed at the wafer-level are disclosed. The method includes providing a magnetic shield at the front side of the chip, back side of the chip, and also in the deep trenches surrounding or adjacent to magnetic tunnel junction (MTJ) array within the prime die region. Magnetic shield in the deep trenches connects front side and back side magnetic shield. This magnetic shielding method is applicable for both in-plane and perpendicular MRAM chips. The MTJ array is formed in the prime die region and in between adjacent inter layer dielectric (ILD) levels of the upper ILD layer in the back end of line (BEOL) of the MRAM chip.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: December 17, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Bharat Bhushan, Juan Boon Tan, Wanbing Yi, Danny Pak-Chum Shum, Shan Gao, Kangho Lee