Patents Examined by Seahvosh Nikmanesh
  • Patent number: 10811354
    Abstract: Embodiments of the present disclosure describe apparatuses, methods, and systems associated with a fuse array of an integrated circuit. An integrated circuit may include a first metallization layer including a plurality of trenches separated by an interlayer dielectric (ILD), wherein the ILD forms a protrusion that extends above a top surface of the trenches. An etch stop layer may be disposed on the first metallization layer. The integrated circuit may further include a fuse disposed on the etch stop layer, wherein the fuse includes a fuse channel coupled between an anode and a cathode, wherein the fuse channel is disposed directly above the protrusion and is in contact with the etch stop layer. The integrated circuit may additionally or alternatively include one or more dummy regions adjacent to the fuse channel and separated from the fuse channel by a dielectric material. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: October 20, 2020
    Assignee: Intel Corporation
    Inventors: Gwang-Soo Kim, Doug B. Ingerly
  • Patent number: 10811501
    Abstract: Methods and apparatus for semiconductor manufacture are disclosed. An example apparatus includes a Gallium Nitride (GaN) substrate; a p-type GaN region positioned on the GaN substrate; a p-type Indium Nitride (InN) region positioned on the GaN substrate and sharing an interface with the p-type GaN region; and a n-type Indium Gallium Nitride (InGaN) region positioned on the GaN substrate and sharing an interface with the p-type InN region.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: October 20, 2020
    Assignee: Intel Corporation
    Inventors: Marko Radosavljevic, Sansaptak Dasgupta, Han Wui Then
  • Patent number: 10804432
    Abstract: A free-standing substrate of a polycrystalline nitride of a group 13 element contains a plurality of monocrystalline particles having a particular crystal orientation in approximately a normal direction. The polycrystalline nitride of the group 13 element is composed of gallium nitride, aluminum nitride, indium nitride or a mixed crystal thereof. The free-standing substrate has a top surface and bottom surface. The free-standing substrate contains at least one of zinc and calcium. A root mean square roughness Rms at the top surface is 3.0 nm or less.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: October 13, 2020
    Assignee: NGK INSULATORS, LTD.
    Inventors: Katsuhiro Imai, Yoshitaka Kuraoka, Mikiya Ichimura, Takayuki Hirao
  • Patent number: 10804626
    Abstract: Implementations of semiconductor packages may include: one or more die electrically coupled to a lead frame. The lead frame may be included within a housing. The semiconductor package may also include a set of signal leads extending from the housing, a set of power leads extending from the housing, and a plurality of press fit pins each fixedly coupled to the set of signal leads and the set of power leads. The set of signal leads and the set of power leads may be configured to couple with a substrate.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: October 13, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jie Chang, Huibin Chen, Tiburcio Maldo, Keunhyuk Lee
  • Patent number: 10803933
    Abstract: A method of forming a self-aligned phase change memory element is provided. A bottom electrode is formed on a landing pad of a phase change memory element. A layer of dielectric material over the bottom electrode and a via etched through the dielectric material to expose the bottom electrode. The via is lined with a GST phase change layer that is etched back from the top surface of the dielectric layer. The via is then filled with a nitride fill, at least of portion of which is etched back from the top surface of the dielectric layer. A top electrode metal is then deposited at the top of the via, wherein the top electrode material is coupled to the phase change material and nitride fill material.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: October 13, 2020
    Assignee: International Business Machines Corporation
    Inventors: Injo Ok, Myung-Hee Na, Nicole Saulnier, Balasubramanian Pranatharthiharan
  • Patent number: 10804118
    Abstract: A die pad is set down at a height lower than a height at which inner leads are provided and a level difference for the set-down becomes larger than a depth of a lower-mold cavity formed in a lower mold. The die pad is placed so that a back surface of the die pad is brought into contact with a lower-mold cavity bottom surface. The lead frame is clamped between the lower mold and an upper mold which has an upper-mold cavity and a suspension-lead relief groove formed to communicate with an end of an opening of the upper-mold cavity to achieve resin encapsulation.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: October 13, 2020
    Assignee: ABLIC INC.
    Inventor: Yasuhiro Taguchi
  • Patent number: 10804036
    Abstract: Capacitors, apparatus including a capacitor, and methods for forming a capacitor are provided. One such capacitor may include a first conductor a second conductor above the first conductor, and a dielectric between the first conductor and the second conductor. The dielectric does not cover a portion of the first conductor; and the second conductor does not cover the portion of the first conductor not covered by the dielectric.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: October 13, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Tae Heui Kwong
  • Patent number: 10796856
    Abstract: The invention provides an aluminum capacitor positive electrode foil product having high voltage resistance and a manufacturing method thereof. the manufacturing method mainly processes an aluminum foil substrate in a vacuum environment and comprises the steps of: heating the aluminum foil substrate; ion bombarding a surface of the aluminum foil substrate to form a pyramid surface layer; reverse sputtering the aluminum foil substrate for surface cleaning, decontamination and degreasing; depositing the aluminum foil substrate by an aluminum target material to form a deposition layer; oxidizing an outer surface of the deposition layer and spraying mixed gases on the outer surface of the deposition layer of the aluminum foil substrate to form an oxidized crystallizing layer; cooling the aluminum foil substrate; and rolling the aluminum foil substrate into a finished product.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: October 6, 2020
    Assignee: Trusval Technology Co., Ltd.
    Inventor: Shih-Pao Chien
  • Patent number: 10796972
    Abstract: A display panel includes first and second test lines connected to the each of data lines, extending in the second direction, and arranged in the first direction, a first test pad electrically connected to the first test line, the first test pad and the first test line being formed from a same layer, and a second test pad electrically connected to the second test line through a contact hole formed through a first insulation layer and disposed adjacent to the first test pad in the second direction.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: October 6, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Ji-Yun Hong, Joon-Geol Kim, Jin-Won Lee, Ki-Won Kim
  • Patent number: 10790427
    Abstract: Disclosed are a lens for a light-emitting device usable in a display apparatus or a lighting apparatus, and a method of manufacturing a light-emitting device package. The lens may include a lens body including a light-receiving portion provided in a lower surface of the lens body, a light-emitting portion provided on an upper surface of the lens body, and a recess provided at a center of the upper surface of the lens body, and a flat portion provided in a horizontal shape on a bottom surface of the recess perpendicularly to a main emission line of light emitted from a light-emitting device to emit at least a part of light received through the light-receiving portion, upward. A diameter of the flat portion may be 1/100 to 1/10 of an inlet diameter of the light-receiving portion.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: September 29, 2020
    Assignee: LUMENS CO., LTD.
    Inventors: Seung Hyun Oh, Yun Geon Cho, Young Mi Na, Byeong Cheol Shim, Bo Gyun Kim, Jong Kyung Lee
  • Patent number: 10790163
    Abstract: In a method for manufacturing a semiconductor sensor, an upper mold has a pair of projections on a wall surface opposing to side surfaces of a semiconductor chip in a first cavity and at positions closest to a second cavity. The projections project so as to reduce the space between the side surfaces of the semiconductor chip and the upper mold, so that a flow of a resin material from a first cavity to a second cavity is delayed. The resin material is filled in the first cavity prior to the second cavity. After a portion of a film corresponding to the first cavity is entirely brought into close contact with the upper mold, the resin material is filled in the second cavity.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: September 29, 2020
    Assignee: DENSO CORPORATION
    Inventor: Masaaki Tanaka
  • Patent number: 10790205
    Abstract: A method includes: forming overlay structures at scribe lines of a wafer, each side of a die region of the wafer is disposed with at least one of the overlay structures, each of the overlay structures comprises at least one feature and at least one recess disposed above the feature, the feature and the recess are respectively disposed at a first and second layers of the wafer, the recess exposes a portion of the feature vertically aligned with the recess; acquiring an image of the overlay structures; measuring a first dimension and a second dimension of a first portion and a second portion of the recess, respectively; determining an overlay between the first and second layers of an edge region of the wafer based on an average of differences between the first and second dimensions; and modifying a subsequent lithography step to compensate for the overlay.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: September 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Feng-Pin Chen, Te-Chia Ku, Chien-Kwen Chen, Chi-Chang Wu, Cheng-Ming Ho
  • Patent number: 10790239
    Abstract: A semiconductor package includes a semiconductor chip having an active surface on which connection pads are disposed and an inactive surface opposing the active surface, an encapsulant disposed to cover at least a portion of the semiconductor chip, and a connection member including a redistribution layer. The redistribution layer includes a plurality of first pads, a plurality of second pads surrounding the plurality of first pads, and a plurality of third pads surrounding the plurality of second pads. Each of the plurality of second pads and each of the plurality of third pads have shapes different from a shape of each of the plurality of first pads. Gaps between the plurality of second pads and gaps between the plurality of third pads are staggered with each other.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: September 29, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae Hyun Lim, Chul Kyu Kim, Kyung Moon Jung, Han Kim, Yoon Seok Seo
  • Patent number: 10784053
    Abstract: Improvements in design and manufacturing techniques to produce a graphene based prismatic supercapacitor of very high capacitance with very high energy density storage able to outperform and replace the cutting edge batteries available in the market today.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: September 22, 2020
    Inventor: Ivan Araujo Dayrell
  • Patent number: 10784183
    Abstract: A semiconductor package includes a semiconductor module, a first package extension frame, a second package extension frame, and a plurality of fasteners. The semiconductor module includes a first side surface, a second side surface, a first major surface, and a second major surface on an opposite side of the semiconductor module from the first major surface. The first package extension frame is configured to attach to the first side surface. The second package extension frame is configured to attach to the second side surface. The plurality of fasteners are configured to mechanically couple the first package extension frame and the second package extension frame to one or more of a circuit board arranged on the first major surface and/or a heat sink arranged on the second major surface.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: September 22, 2020
    Assignee: Infineon Technologies AG
    Inventors: Pawan Garg, Mathias Kiele-Dunsche, Tomas Manuel Reiter, Christopher Roemmelmayer
  • Patent number: 10777560
    Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a semiconductor substrate including a first region and a second region, a dummy separation pattern provided on the second region of the semiconductor substrate to have a recessed region at its upper portion, a first electrode provided on the first region of the semiconductor substrate, a dielectric layer covering the first electrode, a second electrode provided on the dielectric layer, and a remaining electrode pattern provided in the recessed region. The second electrode and the remaining electrode pattern may be formed of a same material.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: September 15, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jonghyuk Park, Byoungho Kwon, Inho Kim, Hyesung Park, Jin-Woo Bae, Yanghee Lee, Inseak Hwang
  • Patent number: 10770388
    Abstract: A semiconductor structure includes a substrate having a first region and a second region, a first source/drain disposed on the substrate in the first region, an interlevel dielectric (ILD) disposed on the source/drain, and a first gate disposed on the substrate. The semiconductor structure further includes a first contact trench within the ILD extending to the first source/drain, a first trench contact within the first contact trench, and a first source/drain contact trench extending to the first trench contact. The semiconductor structure further includes a cross couple contact trench within the ILD, and a cross couple contact disposed in the cross couple contact trench in contact with the first gate and the first trench contact. The cross couple contact couples the first source/drain and the first gate.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: September 8, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruilong Xie, Veeraraghavan S. Basker, Kangguo Cheng, Jia Zeng, Youngtag Woo, Mahender Kumar, Guillaume Bouche
  • Patent number: 10770456
    Abstract: A semiconductor device including a semiconductor substrate is provided. The semiconductor substrate includes a transistor region, and the transistor region includes a drift region, a plurality of trench portions, a plurality of emitter regions and a plurality of contact regions, and an accumulation region provided between the drift region and the plurality of emitter regions in a depth direction, and having a higher first-conductivity-type doping concentration than the drift region. A first outermost contact region is an outermost one of the plurality of contact regions in a direction parallel to the first direction, and a length of the first outermost contact region in the first direction is longer than a length in the first direction of one contact region of the plurality of contact regions other than the first outermost contact region, and the accumulation region terminates at a position below the first outermost contact region.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: September 8, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Soichi Yoshida, Hiroshi Miyata
  • Patent number: 10763229
    Abstract: A semiconductor structure includes a transceiver, a molding surrounding the transceiver, a plurality of vias extending through the molding, and a RDL disposed over the transceiver and the plurality of vias. In some embodiments, the RDL includes an antenna disposed over and electrically connected to the transceiver, and a dielectric layer surrounding the antenna. In some embodiments, the antenna includes an elongated portion extending over the molding and a via portion electrically connected to the transceiver.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: September 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Vincent Chen, Hung-Yi Kuo, Chuei-Tang Wang, Hao-Yi Tsai, Chen-Hua Yu, Wei-Ting Chen, Ming Hung Tseng, Yen-Liang Lin
  • Patent number: 10756283
    Abstract: A sensor including a layer of amorphous selenium (a-Se) and at least one charge blocking layer is formed by depositing the charge blocking layer over a substrate prior to depositing the amorphous selenium, enabling the charge blocking layer to be formed at elevated temperatures. Such a process is not limited by the crystallization temperature of a-Se, resulting in the formation of an efficient charge blocking layer, which enables improved signal amplification of the resulting device. The sensor can be fabricated by forming first and second amorphous selenium layers over separate substrates, and then fusing the a-Se layers at a relatively low temperature.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: August 25, 2020
    Assignee: The Research Foundation for The State University of New York
    Inventors: James Scheuermann, Wei Zhao