Abstract: A semiconductor device is provided including: a semiconductor substrate having a first-conductivity-type drift region; a second-conductivity-type base region provided above the drift region inside the semiconductor substrate; an accumulation region provided between the drift region and the lower surface of the base region inside the semiconductor substrate, and having a lower second-conductivity-type carrier mobility than the drift region and the base region; a gate trench portion provided from an upper surface of the semiconductor substrate to an inside of the semiconductor substrate, where the gate trench portion is in contact with the base region; and a carrier passage region occupying at least a partial region between the accumulation region and the gate trench portion inside the semiconductor substrate, where the carrier passage region has a higher second-conductivity-type carrier mobility than the accumulation region.

Abstract: A structure has a substrate, and a spring structure disposed on the substrate, the spring structure having an anchor portion disposed on the substrate, an elastic material having an intrinsic stress profile that biases a region of the elastic material to curl away from the substrate, and a superconductor film in electrical contact with a portion of the elastic material. A method of manufacturing superconductor structures includes depositing a release film on a substrate, forming a stack of films comprising an elastic material and a superconductor film, releasing a portion of the elastic material by selective removal of the release film so that portion lifts out of the substrate plane to form elastic springs.

Abstract: A neuromorphic device having a synapse array is provided. The synapse array of the neuromorphic device may include an input neuron; an output neuron; and a synapse. The synapse may include a plurality of ferroelectric field effect transistors electrically connected to each other in parallel.

Abstract: Some embodiments include an integrated assembly having a memory array, and having digit lines extending along a first direction through the memory array. Insulative spacers are along sidewalls of the digit lines. The insulative spacers extend continuously along the digit lines through the memory array. Conductive regions are laterally spaced from the digit lines by intervening regions. The conductive regions are configured as segments spaced apart from one another along the first direction. The intervening regions include regions of the insulative spacers and include void regions adjacent the regions of the insulative spacers. The void regions are configured as void-region-segments which are spaced apart from one another along the first direction by insulative structures. Storage-elements are associated with the conductive regions. Some embodiments include methods of forming integrated assemblies.

Abstract: To provide a data processing device using a neural network that can suppress increase in the occupied area of a chip. A product-sum operation circuit is formed using a transistor including an oxide semiconductor having an extremely small off-state current. Signals are input to and output from the product-sum operation circuits included in a plurality of hidden layers through comparators. The outputs of the comparators are used as digital signals to be input signals for the next-stage hidden layer. The combination of a digital circuit and an analog circuit can eliminate the need for an analog-to-digital converter or a digital-to-analog converter which occupies a large area of a chip.

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Upper masses comprise first material laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory blocks and second material laterally-between and longitudinally-spaced-along the immediately-laterally-adjacent memory blocks longitudinally-between and under the upper masses. The second material is of different composition from that of the first material. The second material comprises insulative material. Other embodiments, including method, are disclosed.

Abstract: A method for forming semiconductor devices includes providing a substrate with a conductive pad formed thereon; forming a transparent structure over the substrate, wherein the transparent structure includes a plurality of collimating pillars adjacent to the conductive pad; forming a light-shielding structure over the plurality of collimating pillars and the conductive pad; performing a cutting process to remove one or more materials directly above the conductive pad, while leaving remaining material to cover the conductive pad, wherein the material includes a portion of the light-shielding structure; and performing an etching process to remove the remaining material to expose the conductive pad.

Abstract: After grinding is performed on a semiconductor wafer, the semiconductor wafer is fixed on the electrostatic chuck so as to cause the front surface side of the semiconductor wafer to face the electrostatic chuck. Next, a masking material layer is formed on the rear surface of the ground semiconductor wafer in a state where a surface protection tape is bonded thereto. Then, a masking tape is cut by irradiating, from the rear surface side, portions thereof corresponding to a plurality of streets appropriately formed in a grid shape in a pattern surface with a laser beam so as to form openings for the streets in the semiconductor wafer. Then, SF6 plasma irradiation is performed from the rear surface side so as to etch the semiconductor wafer that has been exposed in the street portions. Finally, ashing is performed using O2 plasma.

Abstract: A silicon carbide semiconductor device includes a first semiconductor layer of a first conductivity type on a substrate of the first conductivity type, a second semiconductor layer of a second conductivity type on the first semiconductor layer, and a first semiconductor region of the first conductivity type. The semiconductor device further includes a gate electrode provided in a plurality of trenches via gate insulating films, a protruding portion disposed on the second semiconductor layer at a bridge area between two adjacent ones of the trenches in a direction orthogonal to the trenches, an interlayer insulating film provided on the gate electrode, and having contact holes that form a striped pattern, a first electrode on the interlayer insulating film and in the contact holes, a plating film provided in a plating area, and a solder on the plating film.

Abstract: A display device comprises a light emitting base layer, a transporting layer, a metal layer and a packaging layer that are sequentially stacked; the transporting layer comprising a conductive lead wire and a test pin; the metal layer comprising a plurality of metal blocks arranged in an array, each of the metal blocks being electrically connected to the test pin through the conductive lead wire; and the packaging layer being used for blocking outside moisture from contacting the metal layer, by testing the electric resistance of the metal block electrically connected to the test pin, determining the moisture blocking effect of the area of the packaging layer corresponding to the metal block. The moisture blocking effect of the area of packaging layer corresponding to the metal block can be determined, and the area where the moisture blocking effect of the packaging layer is poor can be accurately determined.

Abstract: Various embodiments disclose a 3D memory device, including a substrate; a plurality of conductor layers disposed on the substrate; a plurality of NAND strings disposed on the substrate; and a plurality of slit structures disposed on the substrate. The plurality of NAND strings can be arranged perpendicular to the substrate and in a hexagonal lattice orientation including a plurality of hexagons, and each hexagon including three pairs of sides with a first pair perpendicular to a first direction and parallel to a second direction. The second direction is perpendicular to the first direction. The plurality of slit structures can extend in the first direction.

Abstract: Embodiments of three-dimensional (3D) memory devices formed by bonded semiconductor devices and methods for forming the same are disclosed. In an example, a method for forming a bonded semiconductor device includes the following operations. First, a first wafer and a second wafer are formed. The first wafer can include a functional layer over a substrate. Single-crystalline silicon may not be essential to the substrate and the substrate may not include single-crystalline silicon. The first wafer can be flipped to bond onto the second wafer to form the bonded semiconductor device so the substrate is on top of the functional layer. At least a portion of the substrate can be removed to form a top surface of the bonded semiconductor device. Further, bonding pads can be formed over the top surface.

Abstract: A semiconductor substrate in includes a buffer layer and a first crystalline layer. A bandgap of the first crystalline layer is smaller than a bandgap of a second layer. When a semiconductor wafer is formed as a transistor wafer, a channel of a transistor is formed at or near an interface between the first crystalline layer and the second layer. With a first electrode and a second electrode provided and a third electrode provided, when space charge redistribution, for emitting electrons and holes from a bandgap of a crystal positioned in the spatial region, is achieved by applying negative voltage to the third electrode or by applying positive voltage to the second electrode with the first electrode serving as a reference, an electron emission speed in the space charge redistribution is higher than a hole emission speed.

Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate, and the substrate includes a first region and a second region. A gate structure is formed over a fin structure and a first S/D structure has a first volume. A second S/D structure has a second volume, and the second volume is lower than the first volume. A first contact structure is formed over the first S/D structure and a first conductive via is formed over the first contact structure. A power line is formed over the first conductive via, and the power line is electrically connected to the first S/D structure by the first conductive via and the first contact structure.

Abstract: Embodiments herein describe techniques for a semi-conductor device comprising a channel having a first semiconductor material; a source contact coupled to the channel, comprising a first Heusler alloy; and a drain contact coupled to the channel, comprising a second Heusler alloy. The first Heusler alloy is lattice-matched to the first semiconductor material within a first predetermined threshold. A first Schottky barrier between the channel and the source contact, and a second Schottky barrier between the channel and the drain contact are negative, or smaller than another predetermined threshold. The source contact and the drain contact can be applied to a strained silicon transistor, an III-V transistor, a tunnel field-effect transistor, a dichalcogenide (MX2) transistor, and a junctionless nanowire transistor.

Abstract: Embodiments relate to using photocurable polymers to place light emitting diodes (LEDs) onto an electronic display substrate after fabrication of the LEDs. A LED assembly system places LEDs on a temporary substrate after fabrication and applies a a photocurable polymer onto the top surfaces of the LEDs. A transparent pickup head aligns with a subset of the LEDs. The pickup head is positioned on the top surfaces of the subset of LEDs such that the layer of the photocurable polymer is in between the pickup head and the top surface of the subset of the LEDs. Light is directed through the pickup head to cure the photocurable polymer, adhering the subset of LEDs to the pickup head. The subset of LEDs is removed away from the temporary substrate, due to relative movement between the temporary substrate and the pickup head.

Abstract: The present disclosure provides methods for treating film layers in a substrate including positioning the substrate in a processing volume of a processing chamber. The substrate can have high aspect ratio features extending a depth from a substrate surface to a bottom surface. The feature can have a width defined by a first sidewall and a second sidewall. A film with a composition that includes metal is formed on the substrate surface and the first sidewall, the second sidewall, and the bottom surface of each feature. The film in the feature can have a seam extending substantially parallel to the first and second sidewalls. The film is annealed and exposed to an oxygen radical while converting the metal of the film to a metal oxide. The metal oxide is exposed to a hydrogen radical while converting the metal oxide to a metal fill layer.

Abstract: The present application relates to an array substrate, a display panel and a method of manufacturing the same, the array substrate comprising a substrate, a plurality of active switches, a color filter layer, a spacer unit layer, and an electrode layer formed on the color filter layer and the spacer unit layer.

Abstract: A multichip module (MCM) power package includes a multilayer routable leadframe substrate (MRLF) substrate including a first and a second RLF layer. A multilayer extending via extends from the first into the second RLF layer. A first vertical FET has a side flipchip attached to a bottom side of the second RLF. A second vertical FET has a side flipchip attached to a bottom side of the second RLF layer, and contacts the multilayer extending via. A controller integrated circuit (IC) is flipchip attached a top side of the MRLF substrate at least partially over the first vertical FET. A top mold compound is on a top side of the MRLF substrate lateral to the controller IC that is lateral to a metal pad on the multilayer extending via. A bottom side of the first and second vertical FET are exposed by a bottom mold compound layer.

Abstract: Integrated circuit transistor structures are disclosed that include a gate structure that is lattice matched to the underlying channel. In particular, the gate dielectric is lattice matched to the underlying semiconductor channel material, and in some embodiments, so is the gate electrode. In an example embodiment, single crystal semiconductor channel material and single crystal gate dielectric material that are sufficiently lattice matched to each other are epitaxially deposited. In some cases, the gate electrode material may also be a single crystal material that is lattice matched to the semiconductor channel material, thereby allowing the gate electrode to impart strain on the channel via the also lattice matched gate dielectric. A gate dielectric material that is lattice matched to the channel material can be used to reduce interface trap density (Dit). The techniques can be used in both planar and non-planar (e.g., finFET and nanowire) metal oxide semiconductor (MOS) transistor architectures.