Abstract: Aspects of the disclosure provide a method for wafer warpage control. The method includes forming a filling structure in a slit opening on a wafer. Further, the method includes measuring a warpage parameter of the wafer, and determining a thermal profile to adjust a warpage parameter into a target range based on the warpage parameter. Then, the method includes performing a process having the determined thermal profile to adjust the warpage parameter into the target range.

Abstract: A substrate processing system comprising: a first chamber comprising loading tables, on which a plurality of substrates are to be loaded; a second chamber comprising loading tables, on which a plurality of substrates are to be loaded; a first transfer device comprising a plurality of blades configured to hold a plurality of substrates in a lengthwise direction thereof, and configured to transfer a plurality of substrates loaded on the loading tables of the first chamber to the loading tables of the second chamber with the substrates held at the same height; a substrate sensor provided on paths, along which the blades enter the second chamber, and configured to detect a substrate held by the blades; and a controller configured to control the first transfer device.

Abstract: A wafer producing method includes a peel-off layer forming step of applying a laser beam of a wavelength passing through a hexagonal single crystal ingot with a focal point of the laser beam positioned at a depth corresponding to a thickness of a wafer to be produced from an end face of the hexagonal single crystal ingot to form a peel-off layer, a production history forming step of applying a laser beam of a wavelength passing through the wafer with a focal point of the laser beam positioned inside the wafer at a position corresponding to each of a plurality of devices to be formed on a front surface of the wafer to form a production history, and a wafer peeling step of peeling off the wafer from the hexagonal single crystal ingot.

Abstract: Semiconductor manufacturing equipment includes a thickness calculation function, the thickness calculation function including a measurement value acquisition unit configured to acquire a plurality of measurement values at different measurement positions of the wafer from a thickness measurement function configured to measure a thickness of the wafer, a histogram data creation unit configured to create histogram data based on the plurality of measurement values, and a grade group extraction unit configured to extract a grade group from the histogram data, the grade group including sequential grades having frequencies equal to or greater than a predetermined frequency, the thickness calculation function further including a representative value calculation unit configured to calculate a representative value of a thickness of a measurement region based on the grades included in the extracted grade group.

Abstract: A semiconductor device includes a semiconductor substrate including a first conductivity-type impurity, a low-concentration impurity layer including a first conductivity-type impurity having a concentration lower than a concentration of the first conductivity-type impurity in the semiconductor substrate, a backside electrode including a metal material, and first and second transistors in the low-concentration impurity layer. The first transistor includes a first source electrode and a first gate electrode on a surface of the low-concentration impurity layer, the second transistor includes a second source electrode and a second gate electrode on the surface of the low-concentration impurity layer. The semiconductor substrate serves as a common drain region of the transistors.

Abstract: Using measurements from a metrology tool, combinations of tool settings on the metrology tool can be determined. Candidates can then be determined and a response surface model can be generated for each of the candidates. A list of the candidates of the tool settings that provide a maximum response and that are least sensitive to sources of noise can then be determined from the response surface models. The list of the candidates can each be from a denser region of the response surface model.

Abstract: A semiconductor device includes a semiconductor substrate including a first conductivity-type impurity, a low-concentration impurity layer including a first conductivity-type impurity having a concentration lower than a concentration of the first conductivity-type impurity in the semiconductor substrate, a backside electrode including a metal material, and first and second transistors in the low-concentration impurity layer. The first transistor includes a first source electrode and a first gate electrode on a surface of the low-concentration impurity layer, the second transistor includes a second source electrode and a second gate electrode on the surface of the low-concentration impurity layer. The semiconductor substrate serves as a common drain region of the transistors.

Abstract: The present invention adopts an aluminum nitride substrate with great heat dissipation, great thermal conductivity, high electrical insulation, long service life, corrosion resistance, high temperature resistance, and stable physical characteristics. A high-quality zinc oxide film with a wide energy gap is fabricated on the aluminum nitride substrate by magnetron radio frequency (RF) sputtering. Compared with general vapor deposition, chemical vapor deposition and hydrothermal, the magnetron RF sputtering grows the high-quality zinc oxide film with few defects. The zinc oxide film with few defects concentration is an important key technology for short-wavelength optoelectronic devices, which decrease leakage currents of the optoelectronic devices, reduces flicker noise, and further improves its UV-visible rejection ratio.

Abstract: It is provided a layer of a nitride of a group 13 element having a first main face and second main face. The layer of the nitride of the group 13 element includes a first void-depleted layer provided on the side of the first main face, a second void-depleted layer provided on the side of the second main face, and the void-distributed layer provided between the first void-depleted layer and second void-depleted layer.

Abstract: An electronic module has a first substrate 11, a first electronic element 13, a second electronic element 23, a second substrate 21, a first terminal part 110 and a second terminal part 120. The first terminal part 110 has a first terminal base end part 111, a first terminal outer part 113, and a first bending part 112 that is provided between the first terminal base end part 111 and the first terminal outer part 113 and that is bent toward the other side on a side of the first terminal base end part 111. The second terminal part 120 has a second terminal base end part 121, a second terminal outer part 123, and a second bending part 122 that is provided between the second terminal base end part 121 and the second terminal outer part 123 and that is bent toward one side on a side of the second terminal base end part 121.

Abstract: In a teaching method for a transfer mechanism that transfers a substrate to a mounting table, the method includes: transferring an inspection substrate having a plurality of imaging devices on an outer peripheral edge thereof to a transfer position where the substrate is transferred between the transfer mechanism and the mounting table; imaging a part of the mounting table which includes an outer periphery of the mounting table at the transfer position by the imaging devices; calculating a central position of the mounting table based on the image obtained by the imaging devices; and correcting the transfer position based on the central position of the mounting table which is calculated in the calculating and a central position of the inspection substrate at the transfer position.

Abstract: In described examples, a device includes a semiconductor substrate; a buried layer; and a trench with inner walls extending from the buried layer to a surface of the semiconductor substrate, the trench having sidewalls, a bottom wall, a barrier layer including a titanium (Ti) layer covering the sidewalls and the bottom wall, and a filler including more than one layer of conductor material formed on the barrier layer.

Abstract: An electroluminescent device includes a first electrode and a second electrode facing each other; an emission layer disposed between the first electrode and the second electrode and including a plurality of quantum dots and a first hole transporting material having a substituted or unsubstituted C4 to C20 alkyl group attached to a backbone structure; a hole transport layer disposed between the emission layer and the first electrode and including a second hole transporting material; and an electron transport layer disposed between the emission layer and the second electrode.

Abstract: A semiconductor device may include a first cell structure, a second cell structure, a pad structure, a circuit, and an opening. The pad structure may include a first stepped structure and a second stepped structure located between the first cell structure and the second cell structure. The first stepped structure may include first pads electrically connected to the first and second cell structures and stacked on top of each other, and the second stepped structure may include second pads electrically connected to the first and second cell structures and stacked on top of each other. The circuit may be located under the pad structure. The opening may pass through the pad structure to expose the circuit, and may be located between the first stepped structure and the second stepped structure to insulate the first pads and the second pads from each other.

Abstract: An embodiment relates to a device comprising SiC, the device having a p-shield region that is outside a junction gate field-effect transistor region, wherein a doping concentration in a p-well region within a MOSFET channel is non-uniform. Another embodiment relates to a device comprising SiC, the device having a p-shield region, wherein a doping concentration in a p-well region within a MOSFET channel is non-uniform, wherein at least a portion of the p-shield region is located within the p-well region.

Abstract: A method of manufacturing a solid electrolytic capacitor including a porous anode body made of a valve metal having a dielectric film on a surface thereof, and a solid electrolyte layer disposed on a surface of the dielectric film. The method including: a step of; in a liquid including a polyanion and an aqueous medium, polymerizing a monomer compound to obtain a dispersion (1) containing a conjugated electrically conductive polymer and subjecting dispersion treatment to the dispersion (1) to obtain a dispersion (2) containing the conjugated electrically conductive polymer; depositing the dispersion (2) to a porous anode body made of a valve metal having a dielectric coating on a surface thereof; and removing the aqueous medium from the dispersion (2) deposited on the porous anode body to form a solid electrolyte layer, wherein an operation which pauses the dispersion treatment is performed.

Abstract: A method for depositing a boron doped silicon germanium (Si1-xGex) film is disclosed. The method may include: providing a substrate within a reaction chamber; heating the substrate to a deposition temperature; flowing a silicon precursor, a germanium precursor, and a halide gas into the reaction chamber through a first gas injector; flowing a boron dopant precursor into the reaction chamber through a second gas injector independent from the first gas injector; contacting the substrate with the silicon precursor, the germanium precursor, the halide gas and the boron dopant precursor; and depositing the boron doped silicon germanium (Si1-xGex) film over a surface of the substrate.

Abstract: A system for detecting a leak or spill and mitigating losses resulting therefrom comprises a floor covering and a software application. The floor covering includes a sensor assembly, a processing element, and a transmitter. The sensor assembly generates information when exposed to liquid. The processing element determines a location of the liquid based upon the information from the sensor assembly. The transmitter transmits data regarding the liquid. The software application executes on an electronic device and is operable to receive data from the floor covering regarding the liquid; display a message that liquid has been detected on the floor covering; calculate an area of the liquid; determine whether a leak is still occurring and if so, shut an electronically controllable valve; transmit data regarding the liquid to an insurance provider; and/or receive insurance-related information from the insurance provider, such as information related to a proposed insurance claim or estimated damage.

Abstract: A multiple-tool parameter set configuration and misregistration measurement system and method useful in the manufacture of semiconductor devices including using a first misregistration metrology tool using a first set of measurement parameters to measure misregistration between at least two layers at multiple sites on a wafer, including a plurality of semiconductor devices, the wafer being selected from a batch of wafers including a plurality of semiconductor devices intended to be identical to corresponding semiconductor devices on all other wafers in the batch of wafers, thereby generating a plurality of first misregistration data sets, using a second misregistration metrology tool using a second set of measurement parameters to measure misregistration between the at least two layers at multiple sites on a wafer selected from the batch of wafers, thereby generating a plurality of second misregistration data sets, selecting an adjusted first set of modeled measurement parameters associated with the first mis

Abstract: The present technology relates to a semiconductor device, a manufacturing method, and a solid-state imaging device which are capable of suppressing a decrease in bonding strength and preventing a poor electrical connection or peeling when two substrates are bonded to each other. Provided is a semiconductor device, including: a first substrate including a first electrode including a metal; and a second substrate bonded to the first substrate and including a second electrode including a metal. An acute-angled concavo-convex portion is formed on a side surface of a groove in which the first electrode is formed and a side surface of a groove in which the second electrode metal-bonded to the first electrode is formed. The present technology can be, for example, applied to a solid-state imaging device such as a CMOS image sensor.