Patents Examined by Shikha Goyal
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Patent number: 8415992Abstract: An a.c. signal generator is provided with a first circuit (B1) capable of generating alternations of a first a.c. signal (S1) between a first potential (V+) formed by a first voltage source and a second potential (V?). A second circuit (B2) is capable of generating alternations of a second a.c. signal (S2), phase-shifted relative to the first signal (S1), between the first potential (V+) formed by the first voltage source and the second potential (V?). Such a generator can be used, for example, in a flight control calculator of an aircraft.Type: GrantFiled: February 16, 2007Date of Patent: April 9, 2013Assignee: Airbus Operations SASInventor: Olivier Rieux-Lopez
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Patent number: 8400208Abstract: Switch circuits are disclosed, for providing a single-ended and a differentially switched high-voltage output signals by switching a high supply voltage in response to at least one logic-level control signal. The switch that provides the single-ended switched high-voltage output signal includes a chain of at least three serially coupled field effect transistors (FETs). The chain receives the high supply voltage and switches it to output the high-voltage output signal. The switch that provides the differentially switched high-voltage output signal includes two differentially coupled chains, each having at least three serially coupled FETs. The chains receive the high supply voltage and switch it to output the differential high-voltage output signal. A control/bias circuit provides a control voltage to at least one of the FETs in the chains, responsive to the control signal.Type: GrantFiled: December 14, 2011Date of Patent: March 19, 2013Assignee: Synopsys, Inc.Inventors: Agustinus Sutandi, Yanyi L. Wong
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Patent number: 8395433Abstract: A cascoded input-output device is provided configured to receive at an input node a lower voltage input signal and to generate at an output node a higher voltage output signal. The input-output device is split into two voltage domains to enable output signals in a larger range to be generated, while the components of the input-output device individually operate in a smaller range. By applying a selected bias voltage to a protected node of the cascoded input-output device, first changing that selected bias voltage in response to a transition of the input signal and then switching that selected bias voltage back when the output signal reaches a predetermined level, that node is protected, either avoiding stress-inducing voltage swings or providing a switching speed increasing charge boost.Type: GrantFiled: April 20, 2010Date of Patent: March 12, 2013Assignee: ARM LimitedInventors: Mikael Rien, Jean-Claude Duby
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Patent number: 8396416Abstract: The present invention provides a radio system and a method for relaying radio signals. The radio system and the method provide a calibration of transmit radio signals in which no dedicated calibration signal generator is required for calibrating the radio system. The radio system comprises at least one transmit path, a calibration unit at the least one link. A coupled transmit signal is extracted from the transmit paths and selectively forwarded as a feedback signal to a feedback signal demodulator. The feedback signal demodulator generates a base band feedback signal adapted for updating phase and amplitude changes applied a calibrated payload signal.Type: GrantFiled: April 1, 2009Date of Patent: March 12, 2013Assignee: Ubidyne, Inc.Inventor: Peter Kenington
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Patent number: 8395419Abstract: A circuit is constituted by a plurality of n-channel-type transistors, the circuit including: among the plurality of transistors, a transistor including a drain terminal for receiving a voltage of VDD, a source terminal, and a gate terminal for receiving an input signal; among the plurality of transistors, a transistor including a drain terminal for receiving the voltage of VDD, a source terminal connected to an output terminal, and a gate terminal connected to the source terminal of the transistor; and a capacitor provided between a node and a clock terminal for receiving a clock signal. In at least one embodiment, the clock signal inputted into the clock terminal has a frequency higher than that of an output signal outputted from the output terminal.Type: GrantFiled: August 26, 2008Date of Patent: March 12, 2013Assignee: Sharp Kabushiki KaishaInventors: Yuhichiroh Murakami, Yasushi Sasaki, Shige Furuta
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Patent number: 8373461Abstract: A VCO oscillates at a frequency that corresponds to a control voltage. A frequency mixer performs frequency mixing of the output signal of the VCO and a local signal having a local frequency. A first filter extracts a difference frequency signal obtained by the mixing operation of the mixer. A phase difference detection unit makes a comparison between the phase of the difference frequency signal extracted by the first filter and the phase of a reference signal having a reference frequency, and generates a phase difference signal that corresponds to the phase difference. A loop filter performs filtering of the phase difference signal so as to generate the control signal. A second filter extracts a summation frequency signal obtained by the mixing operation of the mixer, and outputs the summation frequency signal via an output terminal thereof.Type: GrantFiled: May 10, 2011Date of Patent: February 12, 2013Assignee: Advantest CorporationInventor: Hideyuki Okabe
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Patent number: 8374542Abstract: A data transmission system transmitting data using a relay is provided. The relay selects a transmission terminal from a plurality of terminals connected to a base station. During a first time slot, the base station transmits base station data to the relay and the transmission terminal transmits terminal data to the relay. The relay transmits the terminal data to the base station and transmits the base station data to the transmission terminal during a second time slot.Type: GrantFiled: July 24, 2012Date of Patent: February 12, 2013Assignees: Samsung Electronics Co., Ltd., Korea University Industrial & Academic Collaboration FoundationInventors: Jun Il Choi, Chang Soon Park, Ki-Hong Park, Young-Chai Ko, Jin Hee Lee
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Patent number: 8359072Abstract: A mobile terminal having a floated display unit is provided. The mobile terminal includes a first body unit having a first surface and a second surface opposite to the first surface, a second body, and a hinge unit. The second body unit is shorter than the first body unit, is disposed in a central part of the first surface of the first body unit, and has a first display unit disposed in a first surface of the second body unit opposite to a second surface of the body unit facing the first surface of the first body unit. The hinge unit connects the first body unit and the second body unit. The second body unit is movable about the hinge unit to open/close the second body unit with respect to the first surface of the first body unit.Type: GrantFiled: November 24, 2008Date of Patent: January 22, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Yasuhisa Kaneda, Jongseong Lee, Yuzuru Masuda
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Patent number: 8358165Abstract: A voltage level shifter having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH) includes a first PMOS transistor and a second PMOS transistor each with a source connected to the VCCH, a gate of the first PMOS transistor being coupled to a drain of the second PMOS transistor, and a gate of the second PMOS transistor being coupled to a drain of the first PMOS transistor. The voltage level shifter further includes a first NMOS transistor with a source connected to a ground (VSS) and a gate connected to a first signal swinging between the VCCL and the VSS, and a first blocking device coupled between the drain of the first PMOS transistor and a drain of the first NMOS transistor, such that the voltage level shifter can operate at a lower VCCL.Type: GrantFiled: November 30, 2011Date of Patent: January 22, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shao-Yu Chou, Yen-Huei Chen, Jui-Jen Wu
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Patent number: 8354863Abstract: A control signal generation circuit includes a voltage detection unit which detects a level of an external voltage and generates first and second detection signals and a control signal control unit which delays a sense amplifier enable signal in response to the first and second detection signals and generates first through third control signals. The enable period of the first and second control signals are controlled based on the levels of the first and second detection signals.Type: GrantFiled: June 29, 2009Date of Patent: January 15, 2013Assignee: Hynix Semiconductor Inc.Inventor: Yin Jae Lee
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Patent number: 8354872Abstract: A switch circuit is disclosed. The switch circuit may include one or more arrangements of transistors coupled in a cascode configuration. The transistors used to implement the switch circuit may be configured for operation within a first range of voltages. The application in which the switch circuit may be implemented may require conveying signals within a second range of voltages that is greater than the first range of voltages. Thus, the switch circuit may include one or more additional transistors to ensure that a voltage drop between any two terminals of the transistors used in the switch circuit is within the first range of voltages.Type: GrantFiled: April 1, 2011Date of Patent: January 15, 2013Assignee: Apple Inc.Inventor: Vincent R. von Kaenel
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Patent number: 8351871Abstract: A method includes receiving a first wireless signal and demodulating data in the first wireless signal using a first demodulation technique. The method also includes receiving multiple second wireless signals simultaneously (where the second wireless signals interfere to produce an interfered signal) and demodulating data in the interfered signal using a second demodulation technique. The method could also include (i) determining that a single transmitter transmitted the first wireless signal and selecting the first demodulation technique in response and (ii) determining that multiple transmitters transmitted the second wireless signals and selecting the second demodulation technique in response. Determining that the single transmitter transmitted the first wireless signal could include determining that a fundamental frequency of the first wireless signal is below a threshold.Type: GrantFiled: April 23, 2009Date of Patent: January 8, 2013Assignee: Honeywell International Inc.Inventors: Haiyang Liu, Henrik Holm
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Patent number: 8351842Abstract: A filtering circuit with a jammer generator cancels a jammer in wireless signals with little degradation of the signal-to-noise ratio (SNR). The filtering circuit may include a jammer generator which acquires information of period and phase of a sinusoidal jammer signal in a composite input sinusoidal signal, which includes the jammer signal and a desired signal, and outputs a pseudo sine-wave with a period and phase corresponding with the period and phase of the jammer signal acquired, and an adder which outputs a difference between the input and output signals of the jammer generator as the desired signal.Type: GrantFiled: May 22, 2012Date of Patent: January 8, 2013Assignees: NEC Corporation, The Board of Trustees of the Leland Stanford Junior UniversityInventors: Shinichi Hori, Boris Murmann
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Patent number: 8344787Abstract: A combination mixer arrangement comprising a first mixer and a second mixer coupled in parallel between first and second input ports and an output port. The mixers are arranged to be driven simultaneously by an input signal provided at the second input port. They are de-coupled, so a bias voltage applied at the first input port provides dc bias simultaneously for the mixers to enable gain expansion of the first mixer responsive to an increase in said input signal and thereby an improved linearity for the combination mixer arrangement.Type: GrantFiled: December 22, 2006Date of Patent: January 1, 2013Assignee: Telefonaktiebolaget L M Ericsson (Publ)Inventors: Mingquan Bao, Yinggang Li
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Patent number: 8344763Abstract: A driver circuit includes an output transistor circuit that includes a first transistor of a first conductivity type and a second transistor of a second conductivity type disposed between a supply voltage source and a reference voltage source, and that outputs an output signal from a connection node between the first transistor and the second transistor, a first pre-buffer circuit that drives a gate of the first transistor in response to an input signal, and a second pre-buffer circuit that drives a gate of the second transistor in response to the input signal.Type: GrantFiled: March 26, 2010Date of Patent: January 1, 2013Assignee: Fujitsu Semiconductor LimitedInventor: Hiromitsu Oosawa
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Patent number: 8344761Abstract: Included are embodiments of a 3-level line driver. At least one embodiment of a method includes generating a repetitive wave; receiving an input signal and a complement of the input signal; providing a 3-level output signal; and filtering a feedback signal, the means for filtering including at least one of the following: a 0th order filter, and an even order filter.Type: GrantFiled: September 11, 2009Date of Patent: January 1, 2013Assignee: Ikanos Communications, Inc.Inventors: Kadaba Lakshmikumar, Sander Laurentius Johannes Gierkink
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Patent number: 8339178Abstract: Level shifter and related apparatus are provided. The level shifter has first to sixth transistors, wherein drains of the first and the second transistors respectively are coupled to drains of the fifth and the sixth transistors as two output nodes of the level shifter, gates of the fifth and the sixth transistors are two input nodes of the level shifter. A source, a drain and a gate of the third transistor are respectively coupled to a gate of the first transistor, the drain of the sixth transistor and a first bias voltage, and a source, a drain and a gate of the fourth transistor are respectively coupled to a gate of the second transistor, the drain of the fifth transistor and a second bias voltage.Type: GrantFiled: August 10, 2011Date of Patent: December 25, 2012Assignee: Orise Technology Co., Ltd.Inventors: Yen-Cheng Cheng, Chien-Chun Huang
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Patent number: 8339161Abstract: A voltage buffer may include a first signal path extending from an input terminal to an output terminal in which the first signal path further may include a buffer transistor that may have a control terminal, and a first and second current terminals responsive to the control terminal. In the first signal path, the control terminal may be connected to the input terminal, the first current terminal may be connected to the output terminal, and the first signal path may supply a load current to a load device responsive to an input signal at the input terminal. The voltage buffer further may include a second signal path extending from the input terminal to a current source node. The second signal path may include a replica load device. The voltage buffer further may include a current source supplying substantially constant current and coupled to the current source node.Type: GrantFiled: July 7, 2009Date of Patent: December 25, 2012Assignee: Analog Devices, Inc.Inventor: Ahmed Mohamed Abdelatty Ali
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Patent number: 8330529Abstract: Embodiments of a method, apparatus and circuit for voltage regulation are disclosed. One embodiment of a circuit includes a first field effect transistor (FET) having a gate, a drain and a source. A current source is connected to the drain of the FET. A second FET has a source connected to the source of the first FET by a node. The second FET also has a gate. A low-pass filter circuit has an input connected to the gate of the first FET and an output connected to the gate of the second FET.Type: GrantFiled: January 28, 2010Date of Patent: December 11, 2012Assignee: Xilinx, Inc.Inventors: Wenfeng Zhang, Qi Zhang
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Patent number: 8324941Abstract: A time-differential analog comparator is disclosed. An example apparatus according to aspects of the present invention includes a source of a variable frequency signal having a frequency responsive to an analog input. A counting circuit is coupled to count cycles of the variable frequency signal. The counting circuit is coupled to count in a first direction for a first time interval and is coupled to count in a second direction opposite to the first direction for a second time interval that occurs after an end of the first time interval. The counting circuit outputs a digital count signal and an evaluation circuit is coupled to generate a decision signal in response to the digital count signal after an end of the second time interval. The first time interval is not equal to the second time interval to generate an offset in the decision signal.Type: GrantFiled: March 1, 2012Date of Patent: December 4, 2012Assignee: Power Integrations, Inc.Inventor: William M. Polivka