Abstract: A DC-coupled two-stage gate driver circuit for driving a junction field effect transistor (JFET) is provided. The JFET can be a wide bandgap junction field effect transistor (JFET) such as a SiC JFET. The driver includes a first turn-on circuit, a second turn-on circuit and a pull-down circuit. The driver is configured to accept an input pulse-width modulation (PWM) control signal and generate an output driver signal for driving the gate of the JFET.

Abstract: A circuit is for generating a signal that indicates whether or not an input current exceeds a pre-established threshold current and, in the affirmative case, that is representative of the difference between the input current and the threshold current. The circuit includes a diode-connected transistor biased with a first constant current in a saturation functioning condition, a sense transistor mirrored to the diode-connected transistor and biased in a linear (triode) functioning condition, a load transistor connected in series to the sense transistor, biased with a second constant current and the control terminal of which is connected in common with the respective terminals of the diode-connected transistor and of the sense transistor. The input current to be compared is injected to a common current node of the load transistor and of the sense transistor, and the output voltage is available on the other current node of the load transistor.

Abstract: Techniques for designing a switchable amplifier are described. In one aspect, a switchable amplifier including a core amplifier circuit configured to selectively enable one or more parallel input transistor pairs is described. The core amplifier circuit comprises a permanently enabled input transistor pair. In another aspect, a device operable between a first mode of operation and a second mode of operation comprising a receiver logic circuit for selectably enabling and disabling a plurality of input transistor pairs within a switchable amplifier is described where the switchable amplifier also includes a core amplifier circuit coupled to the receiver logic circuit for selectably enabling and disabling a transistor pair therein. The described switchable amplifiers result in the ability to provide varying amplifier performance characteristics based upon the current mode of operation of the device.

Abstract: A two-point polar modulator for generating a polar-modulated signal based on an amplitude information and a phase information includes a two-point modulation phase-locked loop which is implemented to enable a frequency setting depending on a first control value via a feedback path of the two-point modulation phase-locked loop and to enable a frequency setting depending on a second control value, directly, bypassing the feedback path, wherein the two-point modulation phase-locked loop is implemented to provide a phase-locked loop output signal depending on the two control values.

Abstract: A method, apparatus, and computer program product, wherein received signal components are determined for a selected group of sub-carriers based on individual noise and signal contributions of the sub-carriers. At least one of noise and a parameter relating to at least one of noise and a signal of a received signal is estimated by combining the determined received signal components depending on a sign of preamble symbols of the sub-carriers.

Abstract: In a load testing system, a transmission device measures a bandwidth of user data transmitted from a user terminal in real time, calculates a calculation bandwidth by subtracting the bandwidth of the user data from an evaluation bandwidth preset to evaluate the performance of a network, and transmits test data corresponding to the calculation bandwidth with the user data corresponding to the bandwidth of the user data. A reception device receives the user data and the test data transmitted with the user data, and evaluates the performance of the network based on the user data and test data.

Abstract: A switched-capacitor circuit including at least one first capacitor and a circuit for switching at least one armature of the first capacitor alternately to one and the other of two terminals at a switching frequency. The circuit further includes a second capacitor connected to the first capacitor at a node; and a filtering circuit connecting the node to a virtual ground only for frequencies belonging to a frequency range.

Abstract: An apparatus for measuring time interval between two selected edges of a clock signal. includes an edge generator, a first multi-tap delay module, a second multi-tap delay module, and a multi-element phase detector. The edge generator produces a first edge at a first output node and a second selected edge at a second output node. First multi-tap delay module provides a first constant incremental delay at each tap to the first edge. Second multi-tap delay module provides a second constant incremental delay at each tap to the second selected edge. Each element of the multi-element phase detector has a first input terminal and a second input terminal. The first input terminal is coupled to a selected tap of the first multi-tap delay module and the second input terminal is coupled to a corresponding tap of the second multi-tap delay module. The output terminals of the multi-element phase detector provide the value of the time interval.

Abstract: A noise generator for generating band-limited noise from a plurality of sinusoidal signals at the same level and equidistant frequency position in the noise spectrum is provided. A noise signal has a low crest factor and for this purpose the phase position of each individual sinusoidal signal is determined.

Abstract: A time-differential analog comparator is disclosed. An example apparatus according to aspects of the present invention includes a source of a variable frequency signal having a frequency responsive to an analog input. A counting circuit is coupled to count cycles of the variable frequency signal. The counting circuit is coupled to count in a first direction for a first time interval and is coupled to count in a second direction opposite to the first direction for a second time interval that occurs after an end of the first time interval. An evaluation circuit is coupled to the counting circuit. The evaluation circuit is responsive to the count of the cycles of the variable frequency signal after an end of the second time interval.

Abstract: An antenna apparatus of a portable terminal and method for implementing characteristics of the antenna apparatus of the portable terminal are disclosed. The antenna apparatus includes a circuit board including a power feeder and a ground, a radiation unit, a power feeder connecting unit for electrically connecting the power feeder to the radiation unit and for feeding electric power to the radiation unit, and a ground connecting unit including at least two paths which have different lengths for electrically connecting the ground to and disconnecting the ground from the radiation unit selectively.

Abstract: An exemplary gate driving circuit is adapted for receiving an external gate power supply voltage and an external control signal, sequentially generating multiple internal shift data signal groups and thereby sequentially outputting multiple gate signals. Each of the internal shift data signal groups includes multiple sequentially-generated internal shift data signals. The gate driving circuit includes multiple gate signal generating modules. Each of the gate signal generating modules includes a voltage modulation circuit and a gate output buffer circuit. The voltage modulation circuit modulates the external gate power supply voltage according to a corresponding one of the internal shift data signal groups and the external control signal, and thereby a modulated voltage signal is obtained. The gate output buffer circuit includes a plurality of parallel-coupled output stages. The output stages output the modulated voltage signal as a part of the gate signals during the output stages being sequentially enabled.

Abstract: A key press detecting circuit for detecting the status of the key is provided. The key press detecting circuit comprises a discharging circuit which discharges when the key (K1) is pressed; and a voltage detecting circuit, which comprises a combination of a PNP transistor (T2) and a NPN transistor (T3), wherein when the discharging circuit discharges for a predefined period, the PNP transistor (T2) will be turn on, which causes the NPN transistor (T3) to be turned on and to output a second signal for a second function.

Abstract: A gate drive apparatus including a constant-current-pulse gate drive circuit which creates a gate signal for a switching device as a constant-current output, a constant-voltage-pulse gate drive circuit which creates the gate signal as a constant-voltage output, and a decision/switch circuit which switches the operation of the constant-current-pulse gate drive circuit and the operation of the constant-voltage-pulse gate drive circuit. The variance of switching speeds attributed to the variances of threshold voltages and mirror voltages in a plurality of switching devices which are driven by the gate drive apparatus can be suppressed, and the variance of losses can be minimized.

Abstract: A CMOS charge pump with improved latch-up immunity is provided. The CMOS charge pump includes a blocking transistor that disconnects first and second boost nodes from a bulk node in response to a blocking control signal, such that a bulk voltage can be maintained at a predetermined level or higher. The CMOS charge pump in a power-up period first precharges the bulk voltage before the main pump performs a boosting operation and prevents a latch-up phenomenon.

Abstract: A large-scale integrated circuit according to the present invention includes a plurality of functional blocks for independently performing a signal processing operation, and a selection controlling circuit for generating a first control signal to select one of the plurality of functional blocks, in which the selection controlling circuit includes a control signal generating circuit for generating a second control signal for stopping the operation of its circuit, and the selection controlling circuit generates the first and the second control signals by a command from a different control circuit.

Abstract: A signal receiver includes a first input terminal, a second input terminal, a first transistor, a second transistor and a variable load. The first and the second transistors each include a gate electrode, a first electrode and a second electrode. The gate electrode of the first transistor is coupled to the first input signal terminal, the gate electrode of the second transistor is coupled to the second input signal terminal, and the variable load is coupled to the first electrode of the first transistor, where a resistance of the first variable load is adjusted to make a DC level at an output node of the signal receiver keep a constant value.

Abstract: A voltage level shifting circuit for an integrated circuit system having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH) is disclosed, the voltage level shifting circuit comprises a pair of cross coupled PMOS transistors connected to the VCCH, a NMOS transistor with a source connected to a ground (VSS) and a gate connected to a first signal swinging between the VCCL and the VSS, and a first blocking device coupled between the drain of the first PMOS transistor and a drain of the first NMOS transistor, the first blocking device being configured to conduct active current when the first signal is in static state or transitions from a logic HIGH to a logic LOW, and the first blocking device being configured to shut off active current when the first signal transitions from the logic LOW to the logic HIGH.

Abstract: Switch circuits are disclosed, for providing a single-ended and a differentially switched high-voltage output signals by switching a high supply voltage in response to at least one logic-level control signal. The switch that provides the single-ended switched high-voltage output signal includes a chain of at least three serially coupled field effect transistors (FETs). The chain receives the high supply voltage and switches it to output the high-voltage output signal. The switch that provides the differentially switched high-voltage output signal includes two differentially coupled chains, each having at least three serially coupled FETs. The chains receive the high supply voltage and switch it to output the differential high-voltage output signal. A control/bias circuit provides a control voltage to at least one of the FETs in the chains, responsive to the control signal.

Abstract: An integrated regulated current drive circuit for driving a squib of an inflatable airbag has a current sense resistor connected in series with a load, and a reference resistor connected in series with a reference current source. Both resistors are matched to define a precise ratio of resistance values which determines the amount of current fed to the squib. Both resistors are implemented by combining a number of identical on-chip resistor elements.