Abstract: A charge domain filter circuit includes a first signal output portion, at least one second signal output, portion, a third signal output portion, and an adder portion. The first signal output portion outputs a first signal that is sampled at a specified time interval. Each second signal, output portion outputs a second signal that is sampled after a specified delay after the first signal is sampled. Where a plurality of the second signal output portions is included, the second signals are sampled in succession. The third signal output portion outputs a third signal that is sampled after a specified delay after the last second signal is sampled. The adder portion adds the first, second, and third signals together and outputs the result. The capacitance ratio of the sampling capacitors in the first signal output portion and the second signal output portion is one of continuously or discretely varied.

Abstract: A switching transistor has its drain and source respectively connected to a gate and a source of an output transistor for supplying output current to a load, and its gate connected to an internal grounding wire GW to be connected to a grounding terminal GND. A resistance element R1 connects the gate to the source of the switching transistor. When a voltage not smaller than a predetermined value is generated across the resistance element R1 at turn-on, due to a parasitic capacitance existing between a power supply terminal. Vcc and the internal grounding wire GW, the switching transistor can be turned on to turn off the output transistor.

Abstract: A comparator comprises a differential amplifier (T1, T2, T8, T9) having differential inputs (IN1, IN2) forming the comparator inputs, and a first and a second amplifier output (f1, f2) forming the comparator outputs of a first comparator stage, wherein the differential amplifier has first (T1, T8) and second (T2, T9) parallel branches. The comparator has a first current source circuit (32) defines a current to be driven through the differential amplifier, a second current source circuit (34) comprising a load driven by the first branch and a third current source circuit (36), comprising a load driven by the second branch. Circuitry (T6,T7) is provided for defining the voltage difference between the first and second amplifier outputs when the differential amplifier is in a stable state providing a differential output. This arrangement drives current through the two branches independently, so that the main transistors in each branch can be kept on to enable rapid response times.

Abstract: In one embodiment, a system includes a replica driver that includes n-type digital-to-analog converter (NDAC) current sources. The replica driver can produce a reference voltage based on current supplied by the NDAC current sources. The system includes driver fingers that are coupled to the replica driver and each include a driver bias circuit and an output driver. The driver bias circuit includes an operational amplifier (op-amp) that can adjust current-source gate voltage in the output driver to produce voltages at output nodes of the driver fingers that approximately match the reference voltage produced by the replica driver.

Abstract: An RF squarer circuit comprises a first RF multiplier and a first variable gain transimpedance amplifier (TIA). The first RF multiplier receives an RF input signal RFIN and provides a first output current. The first TIA receives the first output current as an input. The first TIA provides an output voltage VOUT.

Abstract: Apparatus (40) comprising a multistage charge pump (10) having an output (41) for connecting a load (Cout, KL). The charge pump (10) comprises m gain stages for charging and discharging m external stage capacitors (C) in order to provide an output voltage (Vout) at the output (41) that is about m times higher than a supply voltage (Vdd) of the charge pump (10). The charging and discharging is influenced by switches inside said charge pump (10) that are controlled by a switching signal having a switching frequency (fosc). A monitoring circuit (20) is provided that monitors temperature-induced changes of the value of an external reference capacitor (Cref). Furthermore, means (30) for adjusting the switching frequency (fosc) are employed in order to compensate variations of the gain of said charge pump (10) that are caused by the changes of the value of the m external stage capacitors (C).

Abstract: A setup/hold time control circuit includes a reference signal output unit that sets any one of multiple ports as a reference port and buffers a signal input through the reference port to output as a reference signal. The setup/hold time control circuit also includes a plurality of comparative signal output units that set the remaining ports as comparative ports. The comparative signal output unit synchronizes signals that are input from the comparative ports with the reference signal and outputs the signals as internal signals. The setup/hold time control circuit improves high speed operation of a semiconductor memory device by improving upon the setup/hold time difference between multiple ports.

Abstract: A circuit arrangement for signal mixing. One embodiment provides a circuit arrangement for mixing an input signal with at least one carrier signal. The circuit arrangement includes a current source and a current sink. The current source and the current sink have a mixer core coupled between them which provides cross-coupling between mixer input connections and mixer output connections.

Abstract: An apparatus for generating an internal voltage in a semiconductor integrated circuit includes a first voltage generating unit configured to detect a feedback voltage level of a first internal voltage and perform a pumping operation, thereby generating a first internal voltage, and a second voltage generating unit configured to generate a second internal voltage by detecting a feedback voltage level of the second internal voltage, performing level shifting on the detected feedback voltage level, receiving the first internal voltage, and generating the second internal voltage based on the level shifted feedback voltage signal and the received first internal voltage.

Abstract: A variable transconductance device for a mixer apparatus is provided. The apparatus includes at least one variable current source circuit having a plurality of selectively enabled current source stages. Each of the current source stages, when enabled, is actuable to establish a conductive path between a first supply level and an output terminal. The device further includes at least one variable transconductance circuit having a plurality of selectively enabled transconductance stages. Each transconductance stage, when enabled, is actuable to establish a conductive path between a second supply level and the output terminal. An output current signal is generated at the output terminal responsive to actuation of the variable transconductance circuit by an input voltage signal, whereby the output current signal exhibits a power gain adjustably determined responsive to the numbers of current source and transconductance stages selectively enabled.

Abstract: A circuit design incorporates charge compensation devices within a Track-and-Hold (T/H) circuit to control channel charge generated by a tracking switch. Calibrating a T/H circuit requires selecting charge compensation devices from an array of similar devices to function within the T/H circuit to absorb charge ejected from the tracking switch. The charge compensation devices can also be pseudorandomly selected to operate within the T/H circuit. Charge compensation devices are used to enhance the performance of bottom-plate sampling systems as well as bootstrapped T/H circuits.

Abstract: A system-on-a-chip and a power gating circuit thereof are provided. The power gating circuit includes a first transistor, a charge pump circuit, and a hold circuit. A gate terminal of the first transistor is controlled by a first input signal. A first source/drain terminal of the first transistor is coupled to a first voltage. A second source/drain terminal of the first transistor outputs an output voltage. The charge pump circuit is coupled to a bulk terminal of the first transistor for changing a bulk voltage of the first transistor according to a second input signal. The hold circuit is coupled to the bulk terminal of the first transistor for holding the bulk voltage of the first transistor.

Abstract: A signal detection circuit is used for detecting signal squelch of a differential input signal to generate a corresponding digital output signal. The signal detection circuit includes: a reference voltage generator for generating a reference voltage of which the common mode voltage tracks the common mode voltage of the input signal; a real-time signal judgment circuit, real-time rectifying and amplifying a difference between the input signal and the reference voltage; and a deglitch circuit, sampling and/or amplifying an output signal of the real-time signal judgment circuit, and transforming sampling results into the digital output signal to reflect signal squelch of the differential input signal.

Abstract: A circuit and a method for extending the lifetime of a semiconductor chip. The circuit including a voltage reference generator, a voltage switch, a threshold voltage regulator device and a threshold voltage monitor device tunes an automatic internal power supply. The voltage reference generator provides one or more reference voltage levels that are transmitted to the voltage switch. The threshold voltage monitor device monitors the threshold voltage of the device, triggering the voltage switch to select a reference level for use as a voltage reference for the regulator when the threshold voltage of the monitored device exceeds a predetermined value. The regulator then converts the external power supply to an internal supply and holds it at the predetermined reference level.

Abstract: A multiple-stage charge pump circuit includes first and second pump capacitors, a charge recycle circuit, and first and second transfer circuits. The charge recycle circuit includes first and second driving circuits and a switch circuit turning off to make a node floating and to couple first terminals of the first and second pump capacitors to the node in a first time period. The switch circuit and first and second driving circuits provide a specific voltage to the node and control voltages at the first terminals of the first and second pump capacitors in second and third time periods, respectively. The first and second transfer circuits provide a high voltage to a second terminal of the first pump capacitor in the second time period, and provide the voltage of the second terminal of the first pump capacitor to a second terminal of the second pump capacitor in the third time period.

Abstract: Disclosed herein is a semiconductor integrated circuit including a stoppable circuit unit configured to be alternately switched between a stopped state and an operating state; a first voltage line configured to apply a first voltage to the stoppable circuit unit when the stoppable circuit unit is in the operating state; a second voltage line configured to apply the first voltage to the stoppable circuit unit when the stoppable circuit unit is in a transient state of switching from the stopped state to the operating state; and a third voltage line configured to apply a second voltage to the stoppable circuit unit.

Abstract: A level shifter adaptive for use in a power-saving operation mode is disclosed for interfacing two circuit units powered by a first supply voltage and a second supply voltage respectively. The level shifter includes a preliminary level shifting circuit and an output auxiliary circuit. With the aid of the two supply voltages, the preliminary level shifting circuit is employed to receive an input signal having a first operating voltage swing and functions to convert the input signal into a first output signal and a second output signal both having a second operating voltage swing. The first output signal and the second output signal have opposite voltage levels relative to each other. The output auxiliary circuit is utilized for retaining the voltage level of the first output signal based on the second supply voltage regardless of whether the level shifter is still powered by the first supply voltage or not.

Abstract: An apparatus for an event tolerant circuit including a latch. The event tolerant circuit may maintain correct data values even after the occurrence of an event such as a soft error. The event tolerant circuit may introduce a delay in a feedback loop, thereby passing the glitch value to an element in the feedback loop at different times, thus preventing the propagation of the glitch through the event tolerant circuit.

Abstract: An internal clock generator, system and method of generating the internal clock are disclosed. The method comprises detecting the level of an operating voltage within the system, comparing the level of the operating voltage to a target voltage level and generating a corresponding detection signal, and selecting between a normal clock and an alternate clock having a period longer than the period of the normal clock in relation to the detection signal and generating an internal clock on the basis of the selection.

Abstract: It is made possible to provide a flip-flop circuit capable of implementing the error correction function with a small area increase as far as possible and a pipeline system using such a flip-flop circuit. A flip-flop circuit includes: a flip-flop configured to operate based on a rising edge or a falling edge of a first clock signal; a decision circuit configured to compare an input of the flip-flop with an output thereof and output a request signal when the input of the flip-flop is different from the output thereof; and a control circuit configured to receive a second clock signal from outside and generate the first clock signal and a confirmation signal. When the request signal is sent from the decision circuit after the flip-flop has been activated, the control circuit inverts the first clock signal, sends the confirmation to the decision circuit, and makes the decision circuit cancel the request signal.