Abstract: A charge domain filter circuit includes a first signal output portion, a second signal output portion, and an adder portion. The first signal output portion outputs a first signal that is sampled at a specified time interval. The second signal output portion outputs a second signal that is sampled at the same time interval as the first signal and at a different time. The adder portion adds the first signal and the second signal together and outputs the result. The second signal output portion is capable of selecting the time to sample the second signal from among a plurality of times.

Abstract: A phase shift circuit that includes two, rather than four, delay chains and corresponding selectors is described. This provides a significant area savings and reduces the intrinsic delay of the phase shift circuit, which is particularly beneficial for embodiments in which there is no intrinsic delay matching. In one implementation, the phase shift circuit includes a first delay circuit and a matching delay circuit. The first delay circuit provides a first delay that includes a first intrinsic delay and a first intentional delay. The delay matching circuit provides a matching delay that matches the first intrinsic delay. In one implementation, the phase shift circuit also includes a second delay circuit to provide a second delay that includes a second intrinsic delay and second intentional delay, where the second intrinsic delay matches the first intrinsic delay and the second intentional delay is half as long as the first intentional delay.

Abstract: Disclosed herein are techniques, systems, and methods relating to compensation of phase disturbances of a phase lock-loop during power ramp up or down of a power amplifier. More specifically, a phase lock-loop is described that is able to switch between type I and type II PLL modes depending on the power state of the power amplifier without introducing additional disturbances.

Abstract: An internal voltage generator of a semiconductor device includes a charge pumping unit for performing a charge pumping operation on the basis of the voltage level of a reference voltage to generate a charge pumped voltage having a voltage level higher than the external power supply voltage; and an internal voltage generating unit for performing a charge pumping operation on the basis of an internal voltage level that is linear with respect to a temperature change in a first temperature range to generate an internal voltage, and to perform a charge pumping operation on the basis of an internal voltage clamping level that is constant independent of a temperature change in a second temperature range to generate the internal voltage.

Abstract: A charge pump with a MOS-type capacitor, where the MOS-type capacitor is operated in an inversion region in which capacitance varies as a function of the frequency of the applied signal. The charge pump is switched to transfer charge from an input node to the capacitor and from the capacitor to an output node. During a transition interval, a relatively high frequency switching signal is used to lower the capacitance and increase efficiency. During a settling interval, a relatively low frequency switching signal is used, in which case the capacitance is higher, but similar to a level which would be seen if the capacitor was operated in an accumulation region. MOS capacitor dimensions and switching intervals are mutually optimized to provide high efficiency and required throughput. The charge pump may be configured as a voltage multiplier, divider, inverter or follower, for instance.

Abstract: Transmitter calibration of a wireless device is initiated based upon an operational value of the wireless device. The calibration operations are performed over a plurality of calibration time periods, each calibration time period divided into a plurality of first interval portions interspersed with a plurality of second interval portions, for each calibration time period of the plurality of calibration time periods, respective calibration settings are applied. During the first interval portions substantially fixed first current input is applied to at least one gain adjustable element of the RF circuitry. During the second interval portions, varying current input is applied to the at least one gain adjustable element of the RF circuitry. Output levels of the RF circuitry are measured over the calibration time period. Operational calibration settings for the baseband processing circuitry and analog signal path components of the transmitter are selected based upon the calibration operations.

Abstract: A dynamic clock feedback latch includes a feedback path that generates a data value on an output as a function of data inputs in response to a clock input going low and generates a latching value on the output after a delay from the clock input going high. A first transistor pre-charges a node high while the clock input is low. A second transistor provides a drain path for draining the node low from the pre-charged value while the clock input is high. The output controls a third transistor during the delay to drain the node to a low value if the data value is high and to retain the high value if the data value is low. The feedback path generates the predetermined latching value on the output after the delay to cause an inverted value of the data value to be latched onto the node.

Abstract: A charge pump circuit includes at least one switching transistor and a level-shifter. The level-shifter has a cross-coupled pair of transistors. The level-shifter shifts a voltage of a first input signal to generate a level-shifted signal. The level-shifted signal controls a conductive state of the switching transistor to regulate an output voltage of the charge pump. A feedback loop circuit includes a detector and a charge pump. The detector compares an input signal to a feedback signal to generate first and second output signals. The charge pump includes at least two thin-oxide switching transistors and a level-shifter in another embodiment. The level-shifter shifts a voltage of the first output signal of the detector to generate a level-shifted signal. The two switching transistors are driven by the level-shifted signal and the second output signal of the detector to regulate an output voltage of the charge pump.

Abstract: A voltage controlled oscillator comprising first and second differential delay cells. The first differential delay cell has a first control voltage input terminal. The second differential delay cell is coupled to the first differential delay cell in a loop and has a second control voltage input terminal. The second voltage input terminal is disconnected from the first voltage control input terminal. The first voltage control input terminal receives a first voltage signal, and the second voltage control input terminal receives a second voltage signal different from the first voltage signal.

Abstract: A mixer having high linearity and an associated transconductor combining programmable gain amplifier and mixer functions are provided. The transconductor includes first and second resistors, a differential amplifier, first and second feedback circuits, and first and second transistors. A differential voltage signal is inputted to first and second input ends of the differential amplifier via the first and second resistors. The first and second feedback circuits are provided between a first output end and the first input end, and a second output end and the second input end of the differential amplifier, respectively. The first output end outputs a first output signal for controlling a first current passing through the first transistor. The second output end outputs a second output signal for controlling a second current passing through the second transistor. The first current and the second current determine a differential current.

Abstract: A drive circuit for a power switch component.

Abstract: Described herein are methods and apparatuses for achieving a desired duty cycle on an output of a PLL. According to one embodiment, a method is described, including generating a single ended clock signal from a differential common mode clock signal using a limiting differential amplifier, wherein the single ended clock signal has a duty cycle, generating a differential bias current signal in response to the duty cycle of the single ended clock signal, and correcting the duty cycle of the single ended clock signal to a desired duty cycle by applying the differential bias current signal to the limiting differential amplifier.

Abstract: The invention relates to sample-and hold modules, and notably those which are intended to be placed upstream of an analog-digital converter. The sample-and-hold module conventionally comprises a differential pair of transistors, a follower transistor and a storage capacitor. The follower transistor is turned on during a sampling phase by the application of an emitter current by means of a first current switch and can be disabled during a hold phase by the application of a disabling voltage to its base. The sample-and-hold module operates according to the invention with a hold phase beginning at the same time as the end of a sampling phase and terminating before the start of a new sampling phase. Switching spikes are thus avoided at the transition between the end of a hold phase and the start of a new sampling phase.

Abstract: Embodiments of the invention relate to an integrated circuit comprising at least one functional unit configured to operate at a first clock frequency. The integrated circuit also comprises at least one first interconnect originating from a contact pad and leading to at least one frequency divider configured to receive a clock signal having a second frequency and generate one or more clock signals to operate the functional unit at the first frequency. The integrated circuit further comprises at least one second interconnect coupling an output of the frequency divider and an input of the functional unit, wherein a total length of the second wired interconnect is less than a total length of the first wired interconnects.

Abstract: An enhanced transistor gate drive is disclosed in which a pair of Kelvin sense leads measure the voltage potential across at the gate and source of the transistor. The difference in the voltage potential of the Kelvin sense lead from the gate and the Kelvin sense lead of the source is provided to a voltage controlled current source, which compares the output of the voltage differentiator to an oscillating voltage input. Changes to the voltage difference between the Kelvin sense connectors will result in more or less voltage being applied at the gate of the transistor, thereby parasitic inductance in the transistor from causing the device to switch on and off.

Abstract: It is presented a gate driver circuit for driving an electric switch, the switch being arranged to control a main current using a gate signal. The gate driver circuit comprises: a non-linear capacitor means having a lower capacitance when an applied voltage is under a threshold voltage and a higher capacitance when an applied voltage is over the threshold voltage, wherein the non-linear capacitor is arranged to be connected between a high voltage connection point of the switch and a connection point for the gate signal; a current change rate sensor, the current change rate sensor being configured to detect changes in a main current of the electric switch and to control a gate signal of the electric switch depending on the current change; a gate buffer; and at least one current source, arranged to drive the gate buffer. The current change rate sensor is connected to control the current source to thereby control the gate signal of the electric switch.

Abstract: A circuit to minimize thermally generated offset voltages includes a differential pair of transistors having a first transistor and a second transistor and coupled to a current source, a differential input having a first input coupled to the first transistor and having a second input coupled to the second transistor, a pair of bypass transistors having a first bypass transistor and a second bypass transistor, the first bypass transistor coupled in parallel with the first transistor and the second bypass transistor coupled in parallel with the second transistor, wherein the pair of bypass transistors is coupled to the current source, and control circuitry coupled to the pair of bypass transistors for controlling current through the pair of bypass transistors.

Abstract: A full-wave rectifier circuit receives complementary signals and produces a current corresponding to an added value of differential signals at different levels. A voltage comparator performs a comparison between output signals produced and subjected to current addition and voltage conversion by the full-wave rectifier circuit. A timer detects whether an output signal of the voltage comparator is kept in the same state for a predetermined time or more, and produces a signal indicating a result of the detection. A signal detecting circuit that can accurately identify a state of digital signals of a minute amplitude transferred through a pair of complementary signal lines is achieved without complicating manufacturing steps.

Abstract: A switch circuit is disclosed. The switch circuit may include one or more arrangements of transistors coupled in a cascode configuration. The transistors used to implement the switch circuit may be configured for operation within a first range of voltages. The application in which the switch circuit may be implemented may require conveying signals within a second range of voltages that is greater than the first range of voltages. Thus, the switch circuit may include one or more additional transistors to ensure that a voltage drop between any two terminals of the transistors used in the switch circuit is within the first range of voltages.

Abstract: A start-up reset circuit includes a flip-flop and a clock signal generator. The clock signal generator generates a first clock signal and a second clock signal, wherein there is a phase difference between the first clock signal and the second clock signal. The flip-flop receives an operation voltage and has a setup time, and further includes an input terminal to receive the first clock signal, a clock input terminal to receive the second clock signal, and an output terminal to output a reset signal, wherein the setup time corresponds to the operation voltage.