Abstract: A boost converter includes a clock generator, a switching converter, a hysteretic controller, and a power tracking module. The clock generator configured to output a clock signal; The switching converter configured to operate at a frequency based on the clock signal. The hysteretic controller configured to regulate an intermediate output from the switching converter. The power tracking module configured to change a frequency control signal that is sent to the clock generator, the change in frequency is based on a current flowing into an output capacitor such that a charge time of the capacitor is minimized when the current is maximized.

Abstract: A circuit includes first and second power domains. The first power domain has a first power supply voltage level and includes a master latch, a first level shifter, and a slave latch coupled between the master latch and the first level shifter. The second power domain has a second power supply voltage level different from the first power supply voltage level and includes a retention latch coupled between the slave latch and the first level shifter, and the retention latch includes a second level shifter.

Abstract: Various implementations described herein are directed to a device having multiple stages. The device may have a first stage that provides a data path for an input data signal. The first stage may receive the input data signal, receive feedback signals, and provide an intermediate data signal based on the input data signal and/or the feedback signals. The device may have a second stage that provides set/reset signals based on the intermediate data signal and/or a clock signal. The second stage may receive the intermediate data signal, receive the clock signal, and generate the set/reset signals based on the intermediate data signal and the clock signal. The second stage may also provide the set/reset signals as the feedback signals to the first stage.

Abstract: The present invention provides a technique for a power supply, and particularly, a buck-boost DC-DC converter which is advantageous for energy harvesting from a low voltage. An LC resonant unit generates a pair of clock type signals having phases opposite to each other from an input signal. These signals are supplied to the clock input terminals of the Dickson charge pumps connected in series and converted into power signals having an amplified voltage so as to match the rated input specification of the buck-boost DC-DC converter of a post-stage.

Abstract: A circuit includes a current path and a negative bootstrap circuitry coupled to the current path. The current path is coupled between a floating voltage and a reference ground, and includes a current generator coupled through a resistor to the floating voltage at a first node of the current generator. The current generator is controlled by a pulse signal. The negative bootstrap circuitry includes a pump capacitor coupled to a second node of the current generator and to the reference ground. The pump capacitor is configured to provide a negative voltage at the second node of the current generator based on the pulse signal.

Abstract: A bulk capacitor circuit for an AC input AC/DC Switching Mode Power Supply, such as an AC/DC adapter/charger without active power factor correction, is provided, comprising a plurality of bulk capacitors having different voltage ratings, and driver and control circuitry comprising AC input voltage sensing and comparator circuitry, which enables selective connection of one or more of the plurality of bulk capacitors, responsive to a sensed AC input voltage range. A startup circuit provides power to the driver circuit initially, so that the AC input voltage can be determined before power-up and enabling of the DC/DC converter. This solution provides for a reduction in capacitor volume, with associated improvement in the power density of an isolated AC/DC power supply, while the startup circuit ensures that an appropriate bulk capacitance is connected at startup for low line AC input, to maintain the ripple voltage in an appropriate range for reliable operation.

Abstract: An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.

Abstract: Disclosed is a low power consumption switching circuit with voltage isolation function for a PMOS transistor bulk, including a bulk voltage switching control unit, a bulk voltage switching unit, a first voltage input terminal, a second voltage input terminal, and a bulk voltage output terminal. The bulk voltage switching control unit includes a plurality of PMOS transistors and weak pull-down devices, and is configured to generate a control signal to control the bulk voltage switching unit to make the bulk voltage output terminal to be connected to a higher potential between the first voltage input terminal and the second voltage input terminal. The bulk voltage switching unit includes a plurality of PMOS transistors, and is configured to connect bulks of the PMOS transistors to the higher potential between the first voltage input terminal and the second voltage input terminal. Each of the PMOS transistors is a low-withstand-voltage device.

Abstract: A two-terminal electrical protective device operates by harvesting energy from a small but non-zero voltage drop across a closed solid-state switch. From a default, open-circuit state, the device is remotely triggered by an AC signal to enter the desired conductive state. Power scavenged by an energy harvesting circuit while the device is in the conductive state, powers a gate drive circuit to hold the device in the conductive state for as long as current flows. When current stops, the device returns to the default open-circuit state.

Abstract: A method of generating an output signal based on a single flux quantum (SFQ) pulse includes receiving the SFQ pulse and splitting it into a first path and a second path. The split SFQ pulse of the second path is stored in a latch. A second splitting of the split SFQ pulse of the first path is provided to provide a first output signal and a second output signal of the first path. The second output signal is delayed by a delay Josephson transmission line (JTL). An output of the delay JTL is provided as a clock input to the latch. The first output of the first path is recombined with an output of the latch to provide an output signal.

Abstract: A charge pump for a Radio Frequency Identification (RFID) tag is disclosed. The charge pump includes an antenna port to receive an input AC signal, an input port to receive an input signal, and a main transistor having a gate, a source and a drain. A threshold voltage cancellation circuit is included and is coupled between one terminal of the antenna port and the input port, wherein an output of the threshold voltage cancellation circuit is configured to drive the gate of the main transistor. The threshold voltage cancellation circuit is configured to reduce the threshold voltage of the main transistor when the voltage of the input signal is below a predefined voltage level and to remove threshold voltage cancellation when the voltage of the input signal is above the predefined voltage levels.

Abstract: A negative voltage generation circuit 200 includes a first DC voltage source 201 having a positive terminal connected to a first node N1 (Vin), a first diode 202 having a cathode connected to a negative terminal of the first DC voltage source 201 and an anode connected to an output terminal of a first negative voltage VC1 (fourth node N4), and a first capacitor 204 having a first terminal connected to an output terminal of the first negative voltage VC1 and a second terminal connected to a second node N2 (Vs_high), so as to supply the first negative voltage VC1 to a first driver 20 that performs switching control of a first NMOSFET 11 (first switch element) connected between the first node N1 (Vin) and the second node N2 (Vs_high).

Abstract: Disclosed is a driver stage for activating a first ultrasonic transducer and a method for the operation thereof. The driver stage comprises a first charge pump or power source and a first capacitor. The driver stage also comprises first means for charging the first capacitor with electrical energy from the charge pump and second means for connecting the first capacitor and ultrasonic transducer to different polarities. The first means do not charge the first capacitor with energy from the charge pump or power source when the first capacitor is connected to the ultrasonic transducer by the second means.

Abstract: This application relates to a wide band gap (WBG) power semiconductor system. In one aspect, the system includes a controller configured to generate a switching control signal and a gate driver configured to receive the switching control signal and generate a switching drive signal in response to the switching control signal. The system also includes a WBG power semiconductor device coupled to the gate driver, comprising a gate terminal for receiving the switching drive signal, and configured to be switched in response to the switching drive signal. The switching drive signal has one of three signal levels: a first voltage level higher than a zero voltage level, a second voltage level lower than the zero voltage level, and the zero voltage level at an arbitrary instant. As a result, the gate driver drives the WBG power semiconductor device with the three voltage levels.

Abstract: A semiconductor device that normally-off drives a first transistor that normally-on drives, the semiconductor device includes a first circuitry, a second circuitry, and a first diode. The first circuitry that is connected with a power supply voltage and a ground voltage, detects the power supply voltage, and outputs a transition state of the power supply voltage. The second circuitry that is connected with the power supply voltage, the ground voltage, the first circuitry, and a second transistor, and outputs a drive voltage of a second transistor connected in series with the first transistor, based on an output of the first circuitry. The first diode having an anode connected with a drive terminal of the first transistor and a cathode connected with an output terminal of the second transistor.

Abstract: A switching element control circuit includes: a third electrode voltage control part which controls a third electrode voltage; a first electrode current detection part which detects a first electrode current which flows through the switching element; a memory part which stores information including an initial threshold voltage and an initial first electrode current, and a drain current characteristic of a threshold voltage; and a threshold voltage calculation part which calculates a threshold voltage at a time of operating the switching element based on information including the first electrode current, the initial threshold voltage, and an initial first electrode current, and information relating to the first electrode current characteristic of the threshold voltage, wherein the third electrode voltage control part controls the third electrode voltage based on a threshold voltage at the time of operating the switching element calculated by the threshold voltage calculation part.

Abstract: A sequence circuit (1) includes a detector (2) that detects an occurrence of an event based on an input signal, an acceptor (4) that accepts the event whose occurrence has been detected by the detector, an inhibitor (4) that inhibits the acceptor from accepting another event for a first period using the acceptance of one event by the acceptor as a trigger, a clock pulse generator (3) that generates one or more clock pulses during a period after a second period shorter than the first period elapses from the start of the first period until the first period ends, a determiner (5) that determines a next state based on a current slate and the event accepted by the acceptor, and a latch (6) that latches the next state using the clock pulse. An output of the latch is the current state.

Abstract: Low noise charge pumps are disclosed. In certain embodiments, a charge pump includes a charge pump output terminal that provides a charge pump voltage, a switched capacitor, and a plurality of switches that charge the switched capacitor during a charging operation of the charge pump and that connect the switched capacitor to the charge pump output terminal during a discharging operation of the charge pump. The switches operate with non-overlap between the charging operation and the discharging operation so that the charge pump operates with low noise.

Abstract: A circuit for a multi-voltage input AC/DC charger, such as a Universal AC input AC/DC charger, is provided, comprising a plurality of capacitors having different voltage ratings that are connected in parallel, and a switching circuit comprising input voltage sensing and comparator drive circuitry, to allow for selective connection of one or more of the plurality of capacitors, responsive to a sensed input voltage. Since bulk capacitors occupy a significant proportion of the volume of an AC/DC charger, this solution provides for a reduction in system volume, with associated improvement in the power density of an isolated AC/DC charger.

Abstract: A delay cell includes a cascode transistor and an inverter. The cascode transistor is used to receive a control voltage to generate a bias current, and includes a source terminal, a drain terminal, and a gate terminal receiving the control voltage. The inverter is coupled to the cascode transistor and used to generate an output signal according to the bias current in response to an input signal.