Abstract: A device for demodulating a binary signal having a predetermined carrier frequency and phase-modulated by encoded pulses. The device includes a phase-locked loop circuit having a phase comparator followed by a low-pass filter and a voltage-controlled oscillator, which is voltage-controlled by the output of the filter. The voltage-controlled oscillator outputs a binary signal that is synchronous with the modulated signal and at a frequency N times the carrier frequency. The phase-locked loop circuit also includes a divider that divides by N the output signal of the oscillator and supplies the divided signal to one input of the phase comparator. Thus, a binary signal synchronous with the modulated signal and having a frequency equal to the carrier frequency is supplied to one input of the phase comparator. The other input of the phase comparator receives the modulated signal.

Abstract: An oscillation output generating circuit outputs a voltage V0 as an oscillation output, and a first comparing circuit compares V0 with a constant voltage V1, while a second comparing circuit compares V0 with a constant voltage V2 (<V1). In response to outputs from the first and second comparing circuits, a state maintaining circuit controls the raising/dropping of V0 through the oscillation output generating circuit. When a synchronizing pulse for synchronous oscillation is not inputted, self-advancing oscillation is started, and synchronous oscillation is started otherwise. When the synchronizing pulse is in an active state, a nullifying circuit inhibits transmission of an output from one of the first and second comparing circuits to the state maintaining circuit, whereas the nullifying circuit allows the above transmission when the synchronizing pulse is in an inactive state.

Abstract: A clock generator having a ring structure and a chain structure. The ring structure is formed of an even number of serially connected distributed oscillator elements, and the chain structure is formed of an even number of serially connected distributed oscillator elements. The chain structure is coupled across an odd number of oscillator elements in the ring structure. The ring structure and chain structure, when connected together, generate a clock signal that can be extracted from any of the distributed of oscillator elements.

Abstract: An oscillator having a feedback loop circuit formed by two transductors and one amplifier, and two capacitors respectively connected to the outputs of these transconductors. The transconductors and the amplifier are constructed by common-source configuration transistors to which common bias current is supplied. Since they have invert characteristics for the input voltage, the feedback loop is also self-biased by means of negative feedback operation. The oscillation signal is outputted from an arbitrary position on the feedback loop of the oscillator. According to the oscillator as constituted, the oscillation frequency can be controlled in a wide range by varying the bias current to the common-source transistors.

Abstract: An approach for demodulating a frequency-modulated signal involves processing a frequency-modulated signal with a phase shifter network to provide a demodulated signal that has a relatively constant amplitude around the center frequency of the frequency-modulated signal and that exhibits a relatively linear phase change over an operational frequency range. Embodiments of the invention include a phase shifter network, using N number of cascaded all-pass filters, that receives as an input a limited amplitude signal and outputs a phase-shifted limited amplitude signal that is mixed with the limited amplitude signal. The phase shifter network may also comprise a low-pass bessel filter.

Abstract: A horizontal deflection circuit (61) includes a horizontal oscillator circuit (51) having a horizontal oscillation IC (1). A terminal (T12) of the horizontal oscillation IC (1) is connected to respective first ends of capacitors (8a, 8b). The capacitor (8a) has a second end grounded. The capacitor (8b) has a second end connected to a collector terminal of a transistor (9). The transistor (9) has an emitter terminal grounded through a resistor (11), and a base terminal grounded through a capacitor (13) and connected to a terminal (T121) of a microprocessor (12) through a resistor (14). The horizontal oscillation IC (1) receives a voltage (VT71) at a terminal (T13) thereof and a feedback voltage (VT31) at a terminal (T15) thereof. The circuit (51) generates a signal (VT14) synchronized with a horizontal synchronizing signal (HD) applied to a terminal (T11) to output the signal (VT14).

Abstract: An extremely small and inexpensively manufactured physics package for an atomic frequency standard can be provided with a microwave cavity having non-critical dimensions that is driven in a substantially TEM mode by a lumped LC means, the cavity resonant frequency being primarily determined by the lumped LC means. The lumped LC means can be any structure or combination of elements providing, at a selected microwave reference frequency, a resonant inductance and capacitance. Examples of such lumped LC means include, preferably, a rod or wire conductively attached to a wall of the microwave cavity as a lumped inductance and extending into the cavity to form, at its other end, a gap with an opposing cavity wall as a lumped capacitance; or a pair of rods or wires conductively attached to opposing walls and extending therefrom as a lumped inductance to form a gap therebetween as a lumped capacitance.

Abstract: In a digital demodulator for phase modulated signals, logical values of a waveform-shaped phase-modulated signal are sampled based on a clock signal having a period that stands in integer ratio relationship to a carrier period of the modulated signal and thereafter subjected to serial/parallel conversion for each predetermined interval, whereby a logical pattern of a digital code train subjected to the serial/parallel conversion is analyzed. As a result, phase information required to demodulate digital data can be logically detected.

Abstract: A passive atomic frequency standard such as a Rubidium Frequency Standard or a Cesium Frequency Standard, using a microprocessor or equivalent circuit as part of its Frequency Locked Loop. The microprocessor phase modulates (pm) the RF signal which is introduced into the Atomic Resonator, and demodulates the output signal. The modulation and demodulation are performed by frequency hopping or spread spectrum techniques. Secondly, the microprocessor samples and integrates the error signal from the atomic resonator (Physics Package or Atomic Tube) with a sampled weighted- sum technique and thus better filters the noise, improves the Signal to Noise Ratio, rejects large noise like spikes, etc. Thirdly, the microprocessor saves the last control voltage of the Voltage Controlled Oscillator (VCO) to ease the start-up of the device as well as to keep the VCO at the last frequency in case the atomic resonator fails to function.

Abstract: A high frequency anharmonic oscillator provides a broad band chaotic oscillation with a noise-like spectra. The oscillator output signal is suitable for modulation by data providing for improved secure communication. The chaotic oscillator is based upon a forced second order Duffing equation that is tolerant of delay in the feedback path for high frequency operation.

Abstract: A phase locked loop (1) including an oscillator (5), usually made as a voltage controlled oscillator (VCO), arranged to operate selectively according to different input/output characteristics. The circuit further includes a control circuit (81) for selectively controlling the operation of the oscillator (5) thereby making the oscillator (5) itself operate on one of an optimum characteristic selectively determined according to the operating conditions of the loop (1).

Abstract: A digital phase comparator comprises a first signal input (VCO) and second signal input (REF) as well as a first output (UP+) and second output (DOWN+). It is arranged so as to produce an output pulse (503, 504) to the first output and second output per each of the cycles of the periodic signals (501, 502) brought to the first signal input and second signal input. The duration of the output pulse produced to the first output is longer than the duration of the output pulse produced to the second output when the phase of the periodic signal brought to the first signal input is lagging with respect to the phase of the periodic signal brought to the second signal input. Correspondingly, the duration of the output pulse produced to the first output is shorter than the duration of the output pulse produced to the second output when the phase of the periodic signal brought to the first signal input is leading with respect to the phase of the periodic signal brought to the second signal input.

Abstract: A method for centering the frequency of an injection locked oscillator or (ILO) includes producing measurements of the magnitude and sign of the phase difference between ILO output signals in response to alternate high level and low level RF drive signals, and tuning the center frequency of the ILO in accordance with the measurements to minimize the phase difference.

Abstract: An oscillator circuit for preventing noise from occurring in an output clock signal. The oscillator circuit contains an amplifying unit and a control signal generator. The amplifying unit contains a first amplifying circuit having a first gain and a second amplifying circuit having a second gain connected in parallel. The amplifying unit inputs an oscillating input signal and amplifies it based on an overall gain of the amplifier unit to produce an oscillating output signal. The control signal generator inputs an input control signal and generates an output control signal, and the operational state of the first amplifying circuit is switched when a value of the output control signal switches. The overall gain is based on the first gain when the first operational state of the first amplifying circuit is an enabled state and is not based on the first gain when the operational state of the first amplifying circuit is a disabled state.

Abstract: Method and circuitry for a frequency synthesizer having wide operating frequency range. The frequency synthesizer uses multiple programmable loadable counters in a phase-locked loop arrangement to generate any combination of clock frequencies based on user programmed values. In a specific embodiment of the invention, the phase-locked loop includes a voltage-controlled oscillator with a built-in programmable phase shift. The present invention further provides a preferred embodiment for a high speed loadable down counter for use in the frequency synthesizer.

Abstract: A variable high frequency voltage controlled oscillator (VCO) which is fully integrated. By controlling, with a control voltage, the collector current flowing through one transistor of the integrated oscillator circuit, the diffusion capacitance (also known as base-charging capacitance) of that transistor is varied. Since, in conjunction with an inductance, this capacitance to a large degree determines the frequency of oscillation of the integrated circuit, a fully integrated VCO is made possible.

Abstract: A charge pumping circuit includes a constant current source, a switch element, a first MOS transistor, a second MOS transistor, and a switching-off circuit. The constant current source generates and outputs a current having a constant current value. The switch element is turned on and outputs a current determined by the constant current source when an input signal is active. The first MOS transistor flows the current output from the switch element. The second MOS transistor constitutes a current mirror circuit together with the first MOS transistor, and outputs a current having a current value based on the current flowing through the first MOS transistor, as one of charge and discharge currents. The switching-off circuit turns off the second MOS transistor by charging or discharging the gate when the input signal is inactive.

Abstract: The phase of a pulsed test signal is measured with reference to a reference signal of constant frequency by sampling the test signal at times determined by transitions in the reference signal and comparing the sampled test signal with the output of a phase accumulator clocked by the reference signal. A resulting measurement signal represents a difference in the number of transitions occurring in the sampled test signal and a reference state signal output by the phase accumulator. The measurement signal may be averaged and integrated to obtain an error signal which may then be filtered to provide a control signal for an oscillator. A digital frequency synthesizer is provided by frequency dividing the output of the oscillator by a constant multiple to obtain the test signal and integrating an offset signal in addition to the averaged measurement signal so that the operating frequency of the oscillator is offset from a nominal frequency by an amount determined by the offset signal.

Abstract: An integrated circuit device and method for synthesis of a signal having a desired frequency and low noise. The integrated circuit embodiment of the invention generally includes a phase locked loop (PLL) circuit used in conjunction with a frequency multiplier. Specifically, the integrated circuit embodiment includes a frequency multiplier connected to a first input of a phase detector, a low pass filter connected between the output of the phase detector and the input of a voltage controlled oscillator (VCO), and a frequency divider connected between the output of the VCO and a second input to the phase detector. The frequency multiplier produces a signal having a frequency that is a multiple of the frequency of a reference signal which is connected to the input of the frequency multiplier. For any desired output frequency, use of the multiplier results in a smaller divider ratio "n" in the PLL, thereby reducing the closed loop noise inside the PLL loop bandwidth.

Abstract: A phase-locked loop design is provide that can operate at a plurality of dissimilar supply voltages. By adjusting the frequency range of a PLL based on the power supply voltage, the same PLL design can operate at different supply voltages.