Abstract: An oscillator wherein deviation in the position of a cap of a package is monitored when removing and replacing the cap to adjust the characteristics of the oscillator, and which has stable characteristics. The oscillator comprises a package, a resonator stored in the package, a circuit board and a member for securing the package, the member for securing being attached to the circuit board and contacting two opposing inside faces of the package.

Abstract: A circuit measures a signal propagation delay through a series of memory elements. In one embodiment the memory elements are configured in series so that together they form a delay circuit. In another embodiment the memory elements are configured in a loop to form a ring oscillator. Each memory element propagates a signal to a subsequent memory element so that the time the signal takes to traverse all of the memory elements is proportional to the average delay induced by the individual elements. This proportionality provides an effective means for measuring the delays of those components. Various embodiments of the invention measure the speeds at which memory elements can be preset, cleared, written to, read from, or clock enabled.

Abstract: A signal generator for producing a plurality of signals having the same frequency but a constant phase difference includes first and second cavity oscillators coupled to each other via an appropriate wall and coupling apertures. A first output signal is extracted from the first oscillator at a first predefined location on the oscillator's outer wall, which location defines a first angle relative to the wall aperture which couples the first oscillator to the second. A second output signal is extracted from a predefined location on the outer wall of the second oscillator, which location defines a second angle relative to the aperture in the first oscillator. Because the two oscillators are coupled to each other, they will produce an output signal having substantially the same frequency. The phase difference between the two output signals is defined by the difference between the first and second angles.

Abstract: A low voltage oscillation amplifying circuit including a switching circuit 110 consisting of first and second MOSFETs 1 and 2 of the same conductivity type, which are connected in series and have the gate electrodes connected to each other; and an amplifying circuit 120 including a third MOSFET 3 of a first conductivity type and a fourth MOSFET 4 of a second conductivity type, the gate electrodes of these third and fourth MOSFETs being connected to each other and the drain electrodes of these third and fourth MOSFETs being also connected to each other. The body voltages of the P-type MOSFET 4 and the N-type MOSFET 3 are controlled by a control signal and an inverted signal thereof, respectively. During operation of the amplifying circuit, the threshold voltages of the third and fourth MOSFETs 3 and 4 are made seemingly low, so that the amplifying circuit can be operated at a low voltage.

Abstract: An oscillator circuit for increasing the signal power of a generated oscillating signal while decreasing phase noise. The circuit includes an oscillating stage having an inductor and capacitors for producing a periodic oscillating signal and a first control signal. An active stage having a transistor with a gate terminal, a source terminal and a drain terminal is connected to the oscillating stage so that the first control signal is provided to the source terminal of the transistor. A second control signal is provided to the transistor gate terminal for increasing the voltage applied to the gate terminal when the first control signal decreases the voltage applied to the source terminal, thus controlling the activation of the transistor for supplying signal boosting power to the tank stage.

Abstract: In accordance with the present invention, a frequency modulating phase-locked-loop (FMPLL) (100) architecture is implemented. The frequency of the FMPLL (100) is controlled using a current controlled oscillator (ICO) (126). The ICO (126) receives a current signal incorporating feedback to maintain a fixed gain. The ICO (126) associated with the FMPLL (100) establishes a predictable change in the output frequency for a given change in its input controlled current (ICTL). Relying upon this fixed gain, a frequency shift can be created by summing in an additional delta current (IMOD) to the input control current. By periodically varying the magnitude of the current IMOD, a frequency modulated clock is produced at the output of the ICO 126. The magnitude of IMOD controls the amount of frequency shift of the frequency modulated clock. By providing an IMOD signal which is proportional to the generated system frequency, a frequency shift proportional to the average, or center, frequency is produced.

Abstract: A pulse forming circuit for a vibration type actuator apparatus. This circuit forms pulses by shifting an output from a frequency dividing circuit while changing the shift amount of a time delaying circuit using a ring oscillator for shifting an output from the frequency dividing circuit every time an output is generated by a frequency dividing circuit. With this arrangement, the actuator can be driven by using high-resolution pulse signals.

Abstract: The present invention teaches a system for selectably oscillating at a first or a second oscillating frequency. The system comprises an oscillator for providing an oscillating output. Moreover, the system comprises a switching device for selecting a first or a second impedance in response to a select signal having a voltage. Each of the first and second impedances is fixed independently of the select signal voltage such that the oscillating output oscillates at the first oscillating frequency when the first impedance is provided and oscillates at the second oscillating frequency when the second impedance is provided.

Abstract: A method and apparatus for digitally demodulating QPSK signals includes a first portion in which the digitally sampled data burst is resampled with a plurality of predetermined timing hypotheses. The timing offset is determined according to an analysis of the resampled data. The digitally sampled data burst is then resampled according to the timing estimation. Modulation of the resampled data burst is then removed by twice squaring the complex I/Q pairs. The data with the modulation removed is then subjected to a Chirp-Z Transform to move the data into the frequency domain. The highest spectral power is used to determine the frequency offset. The phase offset is determined and the resampled data burst is derotated and dephased according to the phase offset and the frequency offset.

Abstract: In a phase lock loop, a charge pump includes a current mirror circuit. The current mirror circuit contains a bias current source and a current mirror source which mirrors the current of the bias current source. The current mirror source is turned on and off in accordance with an output signal from a phase detector to produce correction signals for a VCO. To conserve power, circuits are provided for turning the bias current source on just before it is needed by the current mirror source and for turning the bias current source off just after the current mirror source turns off.

Abstract: The invention disclosed herein is a cell construction for use in optically activated atomic frequency standards. The cell includes a stiff non-magnetic metallic chamber body having an integral cold weldable tubulation through which the atomic source material may be charged and the tubulation pinched off to seal the chamber. Optically transparent windows for introducing light radiation into the chamber and receiving light signals generated therein are sealed to the chamber.

Abstract: A method and apparatus for digitally controlling the capacitance of an integrated circuit device using MOS-FET devices. In accordance with one aspect of the present invention, a one-bit or “binary” varactor is presented wherein the gate-to-bulk capacitance of the MOS-FET device exhibits dependency to a D.C. voltage applied between its gate and well implant regions. The capacitance-voltage characteristic of the binary capacitor has three major regions: (1) a first relatively flat region having little or no voltage dependency and having a capacitance equal to a first low capacitance of C1; (2) a sloped region wherein a voltage dependency exists; and (3) a second relatively flat region where there is little or no voltage dependency and where the capacitance equals a second higher capacitance of C2. The capacitance of the binary capacitor can be changed from C1 to C2 simply by changing the polarity of the applied D.C. voltage from a positive to a negative value.

Abstract: Switching a clocked device from an initial frequency to a target frequency includes locking a first phase locked loop (PLL) to the target frequency while a second PLL is driving a clock distribution network at the initial frequency. The first PLL is then substituted for the second PLL on the clock distribution network.

Abstract: A direct modulation multi-accumulator fractional-N frequency synthesizer 1 for generating a carrier signal 150 modulated by a modulation signal 170, 121 is disclosed. The frequency synthesizer includes a Voltage Controlled Oscillator, VCO 50, having a tuning port for controlling the frequency of the signal 110 output by the VCO, a variable divider 20 and a multi-accumulator sequence generator 21 for controlling the variable divider, a reference signal generator 50, a phase detector 30 and a low pass filter 40. These elements are arranged to form a Phase Locked Loop arrangement, the directly modulated output signal of which is taken from the output of the VCO, wherein in-band modulation is performed by varying the variable divider and out-of-band modulation is performed by directly applying the modulating signal to the VCO tuning port.

Abstract: A detector circuit for determining whether synchronization lock has been optimally achieved in feedback-type control systems. The detector circuit evaluates an error signal developed by a phase/frequency detector and compares the absolute magnitude of the error signal to a first threshold signal corresponding to a magnitude metric. When the value of the error signal is less than the magnitude threshold value, an event signal initiates a time interval counter which continues counting so long as the error signal remains below the magnitude threshold value. The time interval counter continues until it counts to a second threshold value corresponding to a timing metric. At this point, synchronization lock is declared.

Abstract: A phase locked loop PLL has a current controlled oscillator ICO, having an input resistance Rin. Rin is proportional to a control current Idac sent to ICO. ICO is coupled to a capacitor, the capacitor and Rin introduce a pole Fpole in the transfer function of PLL. The PLL further has a sigma delta modulator, for providing a digital sigma delta modulated control signal SDO, SDO is converted to an analog control current Idac, that is provided to ICO and smoothed by Rin and the capacitor. The sigma delta modulator forces error signal outside a predetermined frequency BWsd; and Fpole tracks BWsd.

Abstract: A phase-locked loop applied as a phase modulator using an external analog control signal whereby a single-ended pulse-width modulated digital signal may be derived from the phase detector output, and two phase modulated square-wave digital signals may be derived from a reference oscillator and the feedback voltage controlled oscillator. The pulse width modulation and/or phase modulation in power applications can be achieved with far greater speed, precision, simplicity and economy than by existing techniques.

Abstract: A controlled detector circuit for generating a detector current to the input of a selected circuit. An unwanted operational voltage is generated on the input of the selected circuit affecting the precision of the detector circuit. The controlled detector circuit comprises a detector circuit having an RF input for detecting a RF signal and a detector output for providing the detector current. Operation of the detector circuit generates a voltage drop affecting the precision of the detector current. A control circuit having a control output connected to the detector output generates a control voltage for reducing the unwanted parameters affecting the precision of the detector current.

Abstract: A phase interpolation voltage controlled oscillator (VCO). In one embodiment, the VCO is a multiple phase interpolation VCO. The multiple phase interpolation VCO includes a plurality of phase shifting cells each receiving an oscillating signal, and each phase shifting the oscillation signal a different amount. Summing cells receive the phase shifted oscillating signals and combine the signals to determine an output oscillating signal. In one embodiment, further summing cells receive the output of other summing cells to determine the output oscillating signal.

Abstract: A ring oscillator having an odd number of single ended stages, each stage including two transistors connected as a current mirror. The stage provides for low-voltage performance and improved process tolerance characteristics.