Abstract: A crystal oscillation circuit that is capable of operating stably with a low power consumption includes a signal inversion amplifier and a power control circuit that controls the power voltage of this signal inversion amplifier in accordance with an oscillation output. The power control circuit includes a power voltage generation circuit that outputs a plurality of power voltages of different values; a determination control portion that determines the optimal value of the power voltage to be applied to the signal inversion amplifier, based on the oscillation output; and a multiplexer that controls the switching of the power voltage applied to the signal inversion amplifier from the power voltage generation circuit, based on the result of that determination.

Abstract: A semiconductor test structure includes a semiconductor test device having at least one group of test cells that are connected in series and looped back so as to form an oscillator. Each test cell includes a base cell that is formed at least partially in the semiconductor substrate and an ancillary structure that is connected to at least one of the terminals of the base cell. Further, the ancillary structure is distributed over at least two metallization levels that are above the base cell, and is formed on each metallization level by first and second mutually entangled networks of metal tracks that are electrically arranged so as to form an at least capacitive ancillary structure.

Abstract: A frequency generating circuit scales a warp range of a frequency signal. The frequency generating circuit includes a first frequency signal (10) having a first offset signal with a first frequency relationship to the first frequency signal, and a second frequency signal (14). A frequency scaling element (16) receives the first frequency signal (10) and second frequency signal and provides a third frequency signal, such that the third frequency signal includes the first offset signal having a second frequency relationship to the third signal. A switch (54), has a control input (74), a first input for receiving the first frequency signal, a second input operably coupled to the frequency scaling element (16, 42) for receiving the third frequency signal and an output (76) operably coupled to the first input or the second input dependent upon a control signal applied to the control input (74).

Abstract: A current-controlled oscillator (ICO) circuit including an all p-channel transistor based ring oscillator, a first current mirroring stage, and a second current mirroring stage. The all p-channel transistor based ring oscillator, p-channel transistors in the input structure of each amplification stage, and metal lines in the ring and from the ring to the amplification stages over an n-well improve noise immunity and tolerance. The first current mirroring stage utilizes an input current to generate a first voltage controlling a series of differential delay cells connected in a ring topology that forms the ring oscillator. The second mirroring stage utilizes a precision current to generate a second voltage controlling at least one amplification stage, which converts corresponding delay cell output signals to a single-ended logic level signal compatible with external circuitry needs.

Abstract: In a millimeter wave modulation of the direct modulation technology, the switching speed is increased and the modulation bandwidth is broadened. A millimeter wave modulator includes a millimeter wave waveguide. a switching element (PIN diode) disposed in the waveguide in which the switching element is turned on and off by a digital signal to achieve amplitude-modulation of a millimeter carrier wave propagating through the waveguide, and a shunt resistor connected to the switching element in parallel.

Abstract: An oscillator having a tank circuit, an amplifier circuit and a switching circuit. The switching circuit switches the oscillator between a normal power consumption mode and a lower power consumption mode. The amplifier circuit includes an emitter biased transistor. The switching circuit switches between power consumption modes by switching between two selected voltages at the base of the transistor. When in the lower power consumption mode, the oscillator has sufficient current to sustain oscillation but insufficient current to meet the phase noise requirements for good fidelity and high data rates.

Abstract: A circuit for generating a modulated signal contains a reference oscillator for generating a reference signal, a digital synthesis circuit having a clock input and an addition value input for generating a synthesis signal, and a phase comparator for generating a tuning signal depending on the result of a comparison of the phase of the reference signal with the phase of the synthesis signal. An oscillator is provided, which is controlled in a manner dependent on the tuning signal and serves for generating the modulated signal and a further oscillator signal, from which a clock signal present at the clock input of the digital synthesis circuit can be derived. The circuit has a drive device, which generates a digital drive signal from carrier frequency and modulation signals. The drive signal being present at the addition value input of the digital synthesis circuit.

Abstract: A dual-mode multiple signal source/local oscillator module is capable of operating in either an independent offset mode or a common offset mode. The module includes first and second coarse frequency sources, a first signal generator coupled to the first coarse frequency source, a second signal generator, and an offset switch coupled to the second signal generator. The offset switch connects the second signal generator to either the first coarse frequency source in the common offset mode, or the second coarse frequency source in the independent offset mode. Operation of the sources in the common offset mode provides the benefits of dynamic tracking which include reduction of receiver IF phase noise and spurious signal content, improved receiver IF settling speed, and higher measurement accuracy.

Abstract: A phase locked loop frequency source with greatly reduced load pull susceptibility is achieved by using a voltage controlled oscillator of frequency which is neither the same as nor a harmonic or sub-harmonic of the desired output frequency, which is derived by non-integer multiplication from the voltage controlled oscillator frequency.

Abstract: Increase of frequency and reduction of power consumption are advanced for a voltage controlled oscillation circuit. A capacitor C1 is connected between emitters of first and second transistors Tr1, Tr2 to receive an electric current from constant current sources Cs1, Cs2. Also, emitters of third and fourth transistors Tr3, Tr4 receive an electric current from a constant current source Cs3 and have their respective collectors connected through third and fourth resistors R3, R4 to a power supply terminal VCC. The respective collectors and bases of the third and fourth transistors Tr3, Tr4 are connected to bases and collectors of the first and second transistors Tr1, Tr2. Due to this, oscillation outputs are caused at respective ends of the capacitor C1, which has a voltage amplitude equal to a voltage drop due to the third and fourth resistors R3, R4 and values of currents flowing through them. The voltage drop can be decreased to such an extent that the first and second transistors Tr1, Tr2 can be turned on.

Abstract: Of the MOSFETs used to implement an oscillator circuit or a delay circuit in a semiconductor device, minimally the MOSFETs P12 (N12) used in a part of the circuit that affects the oscillation period or delay time are low-threshold-voltage type MOSFETs.

Abstract: An oscillator circuit having a first programmable divider for obtaining a reference signal by dividing the frequency of an oscillation signal of a piezoelectric resonator by a frequency dividing number M. A PLL circuit using the reference signal as input thereto to obtain a multiplied signal, the multiplied signal being formed by multiplying the input signal by a second frequency dividing number N for a second programmable divider provided in a feedback circuit. A third programmable divider capable of dividing the frequency of the multiplied signal by a third frequency dividing number X and outputting the frequency-divided signal. The frequency dividing numbers M, N, and X can be set to values independent of each other. Therefore, innumerable combinations of the frequency dividing numbers M, N, and X can be used and the number of frequencies producible by one oscillator can be largely increased by enabling selection of any suitable one of such combinations.

Abstract: A voltage-controlled oscillator (10), which is comprised of two subcircuits (10a, 10b). Each subcircuit (10a, 10b) has a pair of differentially connected transistors (Q1,Q2 and Q3,Q4). The first subcircuit (10a) is an LC oscillation subcircuit, in which each transistor (Q1, Q2) has a capacitive transformer (C11,C12 and C21,C22) in its feedback loop. The second subcircuit (10b) is a current-controlled variable-capacitance subcircuit, whose feedback loop has a gain that determines the effective capacitance of the subcircuit (10b). When the subcircuits (10a, 10b) are combined, the feedback loops on each side of the differential pairs (Q1,Q2 and Q3,Q4) share the capacitive transformer (C11,C12 and C21,C22). The result is that the effective capacitance determines the oscillation frequency for the oscillator (10).

Abstract: Disclosed is a dual band wireless phone, such as a cellular phone for a mobile communications system, with a dual band transmitter that includes a phase-locked loop (PLL). The dual band transmitter includes first and second power amplifiers and the PLL. The first power amplifier has a first input for a first signal at a first radio frequency band, and a first output for an amplified first signal. The second power amplifier has a second input for a second signal at a second radio frequency band and a second output for an amplified second signal. The outputs of the power amplifiers are connectable to an antenna. The PLL generates two output frequency ranges and includes a voltage-controlled oscillator (VCO) which has a first output connected to the first power amplifier and generates a first signal. A frequency multiplier has an input connected to the first output of the VCO and a second output connected to the second power amplifier.

Abstract: A PLL circuit including multiple sets of phase locked loops, each of which has a phase comparator, a charge pump, a low pass filter, as oscillator, a clock generator and a frequency divider. The various oscillators of the multiple sets each have a different oscillation frequency. The clock generator generates a multiphase clock signal from a single phase clock signal generated by the oscillator. The PLL circuit generates multiple single phase clock signals and multiphase clock signals without need to tune the oscillation frequency of the VCOs over a wide range. The noise of the PLL is reduced since each VCO covers a smaller range of oscillation frequencies.

Abstract: An oscillation circuit including an electrostatic protective circuit connected between a signal path and this constant voltage V.sub.reg. It comprises a first electrostatic protective circuit portion that causes any electrostatic voltage of a first polarity that invades the signal path to be selectively diverted through a diode to the constant voltage V.sub.reg side of the circuit, and any electrostatic voltage of a second polarity that invades the signal path to be selectively diverted through another diode to the ground side. This ensures that the oscillation circuit is not affected by fluctuations in the power voltage from the main power source, enabling it to oscillate at a stable frequency.

Abstract: An improved method and system for generating quadrature phase shift keying signals for use in data transmission is provided. A pair of oscillators are slaved to the transmit frequency and produce two quadrature signal components with the same frequency but 90 degrees out of phase. The two signal components are carried to separate bi-phase switches by mirrored waveguides. Each bi-phase switch has a reflective waveguide coupler which directs the received signal into a waveguide terminated by a hard short and has a controllable shorting plane spaced approximately one-quarter wavelength from the termination point. The shorting planes are controlled by the output data signals and each introduces a 180 degree phase shift in the respective signal component when activated. The reflective couplers direct the selectively phase shifted signal components to an in-phase combiner, where they are combined to produce the quadrature phase shift keyed output signal.

Abstract: There are disposed on a printed substrate a crystal resonator as a piezoelectric resonator, an oscillation circuit, a plurality of surface mount heaters and a temperature controlling circuit for controlling a heating temperature of the heaters. A case of the piezoelectric resonator and a lead terminal of the piezoelectric resonator are heated respectively at the same time by individually separate heaters for the purpose of heating the piezoelectric resonator, the oscillation circuit and the temperature controlling circuit at the same time. Accordingly, it is possible to provide a piezo-oscillator excellent in low power consumption and compactness.

Abstract: A millimeter-wave/microwave oscillator circuit and method of fabricating same are disclosed. A high Q-factor resonator is formed by disposing a transferred electron negative resistance device, such as a Gunn diode, or an IMPATT negative resistance device in a semi-circular cross-sectional shaped resonator cavity. The equivalent capacitance of the negative resistance diode can be designed to resonate with the equivalent series inductance for the resonator cavity by adjusting the dimensions of the cavity and the placement of the negative resistance device therein. Very low cost, compact and lightweight microwave and millimeter-wave integrated circuit power sources using negative resistance diodes can be batch manufactured.

Abstract: A circuit measures a signal propagation delay through a series of memory elements on a programmable logic device. In one embodiment, a number of latches are configured in series. Each latch is initialized to store a logic zero. The first latch is then clock-enabled so that the output of the latch rises to a logic one. The logic one from the first latch clock-enables the second latch in the series so that the output of the second latch rises to a logic one, which in turn enables the next latch in the series. The time required for a rising edge to traverse the entire sequence of latches is the cumulative time required for the output of each latch to change in response to a clock-enable signal. Consequently, the delay through the series of latches provides a measure of the time required for one of the latches to respond to a clock-enable signal.