Abstract: A memory macro includes: word lines; memory cells arranged in an array, the array including rows and columns, the rows corresponding to the word lines, each memory cell being configured to receive a first reference voltage, and each column having voltage supply nodes corresponding to corresponding ones of the memory cells in the column; and switching circuits corresponding to the columns, each switching circuit being configured to selectively provide a first voltage value of a first voltage source or a second voltage value of a second voltage source to the voltage supply nodes; and wherein the first and second voltage values differ by a predetermined voltage value; each of the first and second voltage values is different than a second reference supply voltage; and the word lines are configured to receive the second voltage value as a voltage value representing a high logical value of the word lines.

Abstract: Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically conductive structure is formed within dielectric material providing the memory element in a low resistance state as a result of a first voltage of a first polarity being applied across the electrodes. Additionally, the first electrically conductive structure is removed from the dielectric material providing the memory element in a high resistance state as a result of a second voltage of a second polarity, which is opposite to the first polarity, being applied across the electrodes. A permanent and irreversible electrically conductive structure is formed within the dielectric material providing the memory element in the low resistance state as a result of a third voltage of the second polarity and having an increased potential compared with the second voltage being applied across the electrodes.

Abstract: Provided are a semiconductor memory device and a memory system including the same. The semiconductor memory device includes a power-up signal generator configured to generate a power-up signal in response to a memory voltage reaching a target voltage level, an initializer configured to generate an initialization signal in response to the power-up signal and a reset signal and to generate an initial refresh command in response to completion of an initialization operation, and a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines, the memory cell array configured to perform an initial refresh operation on the plurality of memory cells in response to the initial refresh command.

Abstract: A clock signal is transmitted to first and second integrated circuit (IC) components via a clock signal line, the clock signal having a first arrival time at the first IC component and a second, later arrival time at the second IC component. A write command is transmitted to the first and second IC components to be sampled by those components at respective times corresponding to transitions of the clock signal, and write data is transmitted to the first and second IC components in association with the write command. First and second strobe signals are transmitted to the first and second IC components, respectively, to time reception of the first and second write data in those components. The first and second strobe signals are selected from a plurality of phase-offset timing signals to compensate for respective timing skews between the clock signal and the first and second strobe signals.

Abstract: Apparatuses, methods, and devices that can be utilized to provide temperature-based memory operations are described. One or more apparatuses can include a memory device and a controller coupled to the memory device and configured to: determine an operating temperature of the apparatus, determine one of a plurality of designated open blocks of the memory device to write data based on the operating temperature of the apparatus and a size of the data, and write the data in the determined one of the plurality of designated blocks of the memory device.

Abstract: Methods, systems, and devices for polarity-conditioned memory cell write operations are described. A memory cell may be written with a logic state by performing a write operation that includes applying a first write voltage across the memory cell with a first polarity, and applying a second write voltage across the memory cell after applying the first write voltage of the write operation, the second write voltage of the write operation having a second polarity that is different than the first polarity. In some examples, performing a write operation on a memory cell having different voltage polarities across the memory call may allow such a write operation to be completed in a shorter time than a write operation having a voltage of a single polarity.

Abstract: Memory sense amplifiers and memory verification methods are described. According to one aspect, a memory sense amplifier includes a first input coupled with a memory element of a memory cell, wherein the memory element has different memory states at different moments in time, a second input configured to receive a reference signal, modification circuitry configured to provide a data signal at the first input from the memory element having a plurality of different voltages corresponding to respective ones of different memory states of the memory cell at the different moments in time, and comparison circuitry coupled with the modification circuitry and configured to compare the data signal and the reference signal at the different moments in time and to provide an output signal indicative of the memory state of the memory cell at the different moments in time as a result of the comparison to implement a plurality of verify operations of the memory states of the memory cell at the different moments in time.

Abstract: According to one embodiment, a memory system includes a first nonvolatile memory, and a controller. The controller executes, to the first memory, a program operation first and a first read operation next. The program operation is an operation including (i) acquiring a first temperature, (ii) storing the first temperature, and (iii) controlling the access circuit to set a threshold voltage of a memory cell transistor at a value corresponding to first data. The first read operation is an operation for (i) acquiring a second temperature, (ii) computing a difference between the second and the first temperature, (iii) acquiring a first determination voltage, (iv) correcting the first determination voltage according to the difference, and (v) controlling the first memory to acquire second data corresponding to the threshold voltage on the basis of a comparison between the threshold voltage of the memory cell transistor and the corrected first determination voltage.

Abstract: A memory system includes a nonvolatile memory device including a plurality of memory cells; and a controller including a control unit and a random-access memory, and configured to determine, by applying a program verify voltage to at least one memory cell to be programmed with program data, whether the program data is programmed, wherein the control unit determines percentages of a count of read requests received from a host device and a count of program requests received from the host device, and adjusts a level of the program verify voltage based on the percentages.

Abstract: Apparatuses for receiving an input data signal are described. An example apparatus includes: a plurality of data input circuits and an internal data strobe generator. Each data input circuit of the plurality of data input circuits includes: an amplifier that receives data from a data terminal, and latches the data in an enable state and refrains from latching data in a disable state; and a voltage control circuit coupled to a tail node of the amplifier and provides a first voltage to the tail node during the enable state, and further provides a second voltage different from the first voltage to the tail node in a first mode and to sets the tail node in a floating state in a second mode during the disable state. The internal data strobe signal generator provides a plurality of internal data strobe signals to the plurality of corresponding data input circuits respectively.

Abstract: A resistive memory device includes: a normal cell array suitable for including a plurality of memory cells and generating a cell current according to a resistance state of a memory cell selected based on an input address; a reference cell array suitable for including a plurality of sub-arrays each including a predetermined number of memory cells, and generating a reference current according to a combination of resistance states of memory cells of a sub-array, the sub-array being selected based on a reference selection signal; a sense amplifier circuit suitable for sensing and amplifying a signal indicative of data of the selected memory cell based on the cell current and the reference current during a read operation; and a reference cell selector suitable for generating the reference selection signal, the sub-array in the reference cell array corresponding to a position of the selected memory cell in the normal cell array.

Abstract: A semiconductor device includes: memory cells, first word lined arranged for first ports and each arranging corresponding to respective rows of the memory cells; second word lines arranged for second ports and each arranged corresponding to respective rows of the memory cells, first dummy word lines each provided above the respective first word lines, second dummy word lines each provided above the respective second word lines, a word line driver driving the first and second word lines, and a dummy word line driver driving, in an opposite phase, the second dummy word line for the adjacent second word line according to driving of the first word line from among the first and second word lines, or the first dummy word line for the adjacent first word line according to driving of the second word line from among the first and second word lines.

Abstract: Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a data line, a first memory cell string including first memory cells located in different levels of the apparatus, first access lines to access the first memory cells, a first select gate coupled between the data line and the first memory cell string, a first select line to control the first select gate, a second memory cell string including second memory cells located in different levels of the apparatus, second access lines to access the second memory cells, the second access lines being electrically separated from the first access lines, a second select gate coupled between the data line and the second memory cell string, a second select line to control the second select gate, and the first select line being in electrical contact with the second select line.

Abstract: Subject matter disclosed herein relates to memory devices and, more particularly, to programming a memory cell.

Abstract: A magnetoresistive random access memory (MRAM) includes an MRAM array having MRAM cells, each including a Magnetic Tunnel Junction (MTJ). The MRAM includes data write circuitry configured to write in one-time-programmable (OTP) write mode or in a non-OTP write mode. In the OTP write mode, the data write circuitry is configured to provide a high write voltage magnitude across selected MRAM cells of a first plurality of MRAM cells so as to permanently blow the corresponding tunnel dielectric layers of the selected MRAM cells. In the non-OTP write mode, the data write circuitry is configured to provide a lower write voltage magnitude across selected MRAM cells so as to set a magnetization of the corresponding free layer of each MRAM cell to modulate a resistance of each MRAM cell, without blowing the corresponding tunnel dielectric layer of each MRAM cell.

Abstract: Techniques for suppression of program disturb in flash memory devices are described herein. In an example embodiment, a method for suppression of program disturb in a flash memory array is provided. The flash memory array comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). During a program memory operation, a first voltage, of a selected SG line, and a second voltage, of an unselected BL, are regulated independently of a power supply voltage of the flash memory array, where the first voltage is regulated in a first range of 0.9V to 1.1V and the second voltage is regulated in a second range of 0.4V to 1.2V.

Abstract: A nonvolatile memory device includes a memory cell array and a control circuit. The memory cell array includes a plurality of memory blocks, each including a plurality memory cells coupled to word-lines respectively, and the word-lines are stacked vertically on a substrate. The control circuit divides a first memory block of the plurality of memory blocks into a partial bad region and a partial normal region based on error information of an uncorrectable error of the first memory block which is designated as a bad block. The control circuit performs a memory operation on the partial normal region by applying a first bias condition to the partial bad region and by applying a second bias condition to the partial normal region, based on a command and an address, and the first bias condition is different from the second bias condition.

Abstract: One or more write operations are performed on a memory component. A determination is made as to whether a number of the plurality of write operations performed on the memory component since performance of a refresh operation on the memory component exceeds a threshold value. In response to determining that the number of write operations performed on the memory component exceeds the threshold value, a memory cell of the memory component is identified based on the plurality of write operations. Data stored at memory cells of the memory component that are proximate to the identified memory cell is refreshed.

Abstract: An indication that a test resource of a test platform has failed can be received. The test resource can be associated with performing a portion of a test of memory components. A characteristic of the test resource that failed can be determined. Another test resource of the test platform can be identified based on the characteristic of the test resource that failed. The portion of the test of memory components can be performed based on the another test resource of the test platform.

Abstract: A controller controls an operation of a semiconductor memory device including a plurality of memory blocks. The controller includes a temperature sensing unit, a period storage unit, and a command generating unit. The temperature sensing unit generates temperature information by sensing a temperature of the semiconductor memory device. The period storage unit updates an output period of a dummy read command that allows the semiconductor memory device to perform a dummy read operation, based on the temperature information. The command generating unit generates the dummy read command, based on the output period.