Abstract: Techniques for reducing program disturb of memory cells which are formed in a two-tier stack, when a selected word line is in the upper tier. In one approach, at the start of the program phase of a program loop, voltages of word lines adjacent to the interface are increased to a pass voltage before voltages of remaining word lines are increased to a pass voltage. This delay provides time for residue electrons in the lower tier to move toward the drain end of a NAND string to reduce the likelihood of program disturb. In another approach, the voltages of the word lines adjacent to the interface are maintained at 0 V or other turn-off voltage during the program phase to block the passage of residue electrons from the lower tier to the upper tier.

Abstract: Systems, apparatuses, and methods related to subrow addressing for electronic memory and/or storage are described. Independent subrow addressing may enable energy consumed by performance of an operation on a particular subset of data values stored by a row to more closely correspond to the size of the particular subset of data values relative to energy consumed by addressing and activating the complete row. For instance, one such apparatus includes a plurality of subrows within a row of memory cells and a controller configured to selectably address and manage an activation state of each subrow of the plurality of subrows. The apparatus further includes subrow driver circuitry coupled to the controller. The subrow driver circuitry is configured to maintain one or more subrows of the plurality in the activation state based at least in part on signaling from the controller.

Abstract: A memory system includes a nonvolatile memory device including a plurality of memory cells; and a controller including a control unit and a random-access memory, and configured to determine, by applying a program verify voltage to at least one memory cell to be programmed with program data, whether the program data is programmed, wherein the control unit determines percentages of a count of read requests received from a host device and a count of program requests received from the host device, and adjusts a level of the program verify voltage based on the percentages.

Abstract: A semiconductor integrated circuit according to an embodiment includes: first to third wiring lines; first memory elements disposed in a cross region between the first wiring lines and the second wiring lines; second memory elements disposed in a cross region between the first wiring lines and the third wiring lines; a first write control circuit connected to the first wiring lines: a first circuit connected to one of the second wiring lines and supplying a first potential; a second circuit connected to the other one of the second wiring lines and supplying a second potential lower than the first potential; SRAM cells connected to the third wiring lines; and a selection circuit including input terminals electrically connected to the first wiring lines and an output terminal, the selection circuit connecting one of the input terminals to the output terminal in accordance with an input signal.

Abstract: Apparatuses and methods for providing an indicator of operational readiness of various circuits of a semiconductor device following power up are described in the present disclosure. An example apparatus includes a first circuit configured to receive a supply voltage and further configured to provide an active first signal responsive to the supply voltage exceeding a threshold voltage. The example apparatus further includes a second circuit coupled to the first circuit and activated by the active first signal, the second circuit configured to provide an active second signal when a third circuit is ready for operation.

Abstract: A semiconductor memory device may include a memory circuit including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines, and configured to output data from the memory cell coupled to each of the bit lines through a global input/output line; a flag-generating circuit configured to generate a flag signal received with respect to the bit lines. The flag signal may include at least one of a duplicate data flag signal and a data bus inversion flag signal based on number of data having a specific logic level among the data in the memory cell for each of the bit lines that may be provided through the global input/output line in a read operation; and an output circuit configured to output the data based on at least one of the duplicate data flag signal and the data bus is inversion flag signal.

Abstract: Methods, systems, and devices for tapered memory cell profiles are described. A tapered profile memory cell may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a bottom surface and a top surface opposite the bottom surface. In some cases, the self-selecting memory component may taper from the bottom surface to the top surface. In other examples, the self-selecting memory component may taper from the top surface to the bottom surface. The top surface of the self-selecting memory component may be coupled to a top electrode, and the bottom surface of the self-selecting memory component may be coupled to a bottom electrode.

Abstract: Apparatuses and methods for self-refreshing a plurality of dies are described. An example apparatus includes a first die including a first bank and a second bank, the first bank and the second bank including memory cells; and a second die vertically slacked with the first die, the second die including a third bank and a fourth bank, the third bank and the fourth bank including memory cells. The third bank is vertically aligned with the first bank. The first bank and the fourth bank are configured to be refreshed prior to refreshing the second bank and the fourth bank.

Abstract: Apparatuses and methods are provided for reversing data stored in memory. An example apparatus comprises an array of memory cells, a first plurality of sensing components corresponding to a respective first plurality of columns of the array, a second plurality of sensing components corresponding to a respective second plurality of columns of the array, and a plurality of shared input/output (I/O) lines (which may be referred to as SIO lines). Each one of the plurality of SIO lines can be selectively coupled to a respective subset of the first plurality of sensing components and to a respective subset of the second plurality of sensing components. The apparatus can include a controller configured to control reversing a logical sequence of data stored in a group of memory cells coupled to a first access line of the array by performing a plurality of transfer operations via the plurality of SIO lines.

Abstract: An address decoder and a semiconductor memory device including the same are disclosed, which relate to a technology for a decoding circuit configured to decode a column address. The address decoder includes a pre-decoder and a column decoder. The pre-decoder divides a plurality of pre-decoding signals into at least one column address group by decoding column addresses, outputs the pre-decoding signals for each group, and outputs a second pre-decoding signal group which is an inverted signal of a first pre-decoding signal group from among the plurality of pre-decoding signals. The column decoder outputs column selection signals by decoding the plurality of pre-decoding signals in a manner that operation of a metal oxide semiconductor (MOS) transistor is controlled by the first pre-decoding signal group and the second pre-decoding signal group.

Abstract: A memory device comprising an array of memory cells wherein each memory cell comprises a respective magnetic random access memory (MRAM) element, a respective gating transistor, and a common wordline coupled to gates of gating transistors of said array of memory cells. The memory device further comprises a common source line coupled to sources of said gating transistors, wherein said common source line is routed perpendicular to said plurality of bit lines within said array of memory cells, and a plurality of bit lines which are routed parallel to each other and connected to the drains of said gating transistors, wherein each bit line is associated with a respective memory cell of said array of memory cells.

Abstract: A memory device comprising an array of memory cells wherein each memory cell includes a respective magnetic random access memory (MRAM) element, and a respective gating transistor. A plurality of bit lines are routed parallel to each other, wherein each bit line is associated with a respective memory cell of the array of memory cells. A common word line is coupled to gates of gating transistors of the array of memory cells. A common source line is coupled to sources of the gating transistors, wherein the common source line is routed perpendicular to the plurality of bit lines within the array of memory cells. A sacrificial circuit element is coupled to a sacrificial bit line, coupled to the common word line and coupled to the common source line, wherein the sacrificial circuit element is operable to provide a desired voltage to the common source line wherein the desired voltage originates from the sacrificial bit line.

Abstract: Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically conductive structure is formed within dielectric material providing the memory element in a low resistance state as a result of a first voltage of a first polarity being applied across the electrodes. Additionally, the first electrically conductive structure is removed from the dielectric material providing the memory element in a high resistance state as a result of a second voltage of a second polarity, which is opposite to the first polarity, being applied across the electrodes. A permanent and irreversible electrically conductive structure is formed within the dielectric material providing the memory element in the low resistance state as a result of a third voltage of the second polarity and having an increased potential compared with the second voltage being applied across the electrodes.

Abstract: Disclosed are methods, systems and devices for operation of dual non-volatile memory devices. In one aspect, a pair of non-volatile memory device coupled in series may be placed in complementary memory states any one of multiple memory states in a write operation by controlling a current and a voltage applied to terminals of the non-volatile memory device.

Abstract: A semiconductor device includes a clock gating tree comprising a first clock gating stage and a second clock gating stage. The first clock gating stage is configured to receive an activate detection signal and to activate clocking events in the second clock gating stage in response to the activate detection signal. The clocking events are not activated in the absence of the activate detection signal.

Abstract: A device includes an array of memory cells, input/output lines coupled to the memory cells, and sense amplifiers coupled to the input/output lines. Each sense amplifier is associated with a respective input/output line. The device also includes trim circuits. Each trim circuit is associated with and coupled to a respective sense amplifier. Each sense amplifier receives a respective reference voltage that allows the sense amplifier to sense a bit value of an addressed memory cell. Each trim circuit is operable for compensating for variations in the reference voltage used by the respective sense amplifier.

Abstract: According to one embodiment, a semiconductor memory of an embodiment includes memory cells, a word line, bit lines, and a controller. The word line is coupled to a plurality of memory cells. The plurality of bit lines are respectively coupled to the plurality of memory cells. The controller executes a first write, and classifies a plurality of memory cells to which the second data should be written into a plurality of subgroups in accordance with a result of the first write, and after the classification, the controller executes a second write that includes a first program loop.

Abstract: Methods, systems, and devices for polarity-conditioned memory cell write operations are described. A memory cell may be written with a logic state by performing a write operation that includes applying a first write voltage across the memory cell with a first polarity, and applying a second write voltage across the memory cell after applying the first write voltage of the write operation, the second write voltage of the write operation having a second polarity that is different than the first polarity. In some examples, performing a write operation on a memory cell having different voltage polarities across the memory call may allow such a write operation to be completed in a shorter time than a write operation having a voltage of a single polarity.

Abstract: Apparatuses for receiving an input data signal are described. An example apparatus includes: a plurality of data input circuits and an internal data strobe generator. Each data input circuit of the plurality of data input circuits includes: an amplifier that receives data from a data terminal, and latches the data in an enable state and refrains from latching data in a disable state; and a voltage control circuit coupled to a tail node of the amplifier and provides a first voltage to the tail node during the enable state, and further provides a second voltage different from the first voltage to the tail node in a first mode and to sets the tail node in a floating state in a second mode during the disable state. The internal data strobe signal generator provides a plurality of internal data strobe signals to the plurality of corresponding data input circuits respectively.

Abstract: According to one embodiment, a magnetic memory includes: magnetoresistive effect elements arranged on an conductive layer; and a first circuit which passes a write current through the conductive layer and applies a control voltage to the magnetoresistive effect elements, to write data including a first value and a second value into the magnetoresistive effect elements. The first circuit adjusts at least one of a write sequence of the first value and the second value, a current value of the write current, and a pulse width of the write current, on the basis of an arrangement of the first value and the second value in the data.