Patents Examined by Son L. Mai
  • Sensing techniques for multi-level cells
    Patent number: 10535397
    Abstract: Techniques are provided for sensing a memory cell configured to store three or more states. A charge may be transferred between a digit line and a node coupled with a sense component using a charge transfer device. During a single read operation, multiple voltages may be applied to the gate of the charge transfer device. The node may be sensed a number of times based on a number of voltages applied to the gate of the charge transfer device. The charge may be transferred by the charge transfer device based on a value of the signal on a digit line and a voltage applied to the gate of the charge transfer device. Based on the charge being transferred and the sense component sensing the node multiple times, a logic state associated with the memory cell may be determined.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: January 14, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Christopher John Kawamura, Scott James Derner
  • Current-mode sense amplifier
    Patent number: 10529388
    Abstract: A current sense amplifier is provided. The amplifier comprises a first cross coupled inverter, a second cross coupled inverter, and a transmission gate. The first cross coupled inverter has a first source coupled to sense current input. The second cross coupled inverter has a second source coupled to a reference current input. The transmission gate comprises a first transmission end, a second transmission end, and a gate input. The first transmission end is operatively coupled to a first input of the first cross coupled inverter. The second transmission end is operatively coupled to a second input of the second cross coupled inverter. The gate input is operatively coupled to the control line input. Each cross coupled inverter is configured for switching a coupling of the sense current input and the reference current input.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: January 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Alexander Fritsch, Michael Kugel, Juergen Pille, Dieter Wendel
  • Semiconductor memory device
    Patent number: 10522198
    Abstract: A semiconductor memory device includes a sense amplifier, a voltage supply circuit and a voltage supply control circuit. The sense amplifier may be activated by receiving driving voltages from first to third voltage supply lines to detect and amplify voltage levels of a data line and a data bar line. The voltage supply circuit may apply the driving voltages to the first to third voltage supply lines in response to first to third voltage supply signals and a bias control signal. The voltage supply control circuit may generate the first to third voltage supply signals and the bias control signal in response to an active signal.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: December 31, 2019
    Assignee: SK hynix Inc.
    Inventor: Hyung Sik Won
  • Integrated circuits having memory cells with shared bit lines and shared source lines
    Patent number: 10510392
    Abstract: Integrated circuits, memory arrays and methods for operating integrated circuit devices are provided. In an embodiment, an integrated circuit includes a selected column of bit cells, wherein each bit cell in the selected column is coupled to a source line and coupled to a bit line. Further, the integrated circuit includes a first column of bit cells laterally adjacent the selected column, wherein each bit cell in the first column is coupled to the source line. Also, the integrated circuit includes a second column of bit cells laterally adjacent the selected column, wherein each bit cell in the second column is coupled to the bit line.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: December 17, 2019
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Bipul C. Paul, Akhilesh Jaiswal, Ajey Poovannummoottil Jacob, William Taylor, Danny Pak-Chum Shum
  • Memory device performing test on memory cell array and method of operating the same
    Patent number: 10510429
    Abstract: A memory device including a memory cell array connected to a first bit line, first word lines, and second word lines, the memory cell array including a first memory cell and a second memory cell, the first memory cell being connected between the first word lines and the first bit line, and the second memory cell being connected between the second word line and the first bit line; a first word line driver configured to drive the first word lines; a second word line driver configured to drive the second word lines; and a test manager configured to drive second word lines to change a capacitance of the first bit line, and after the capacitance of the first bit line is changed, drive first word lines to test the first word lines.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: December 17, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-yong Choi, Kyung-ryun Kim, Woong-dai Kang, Hyun-chul Yoon
  • Volatile memory device with automatic lower power state
    Patent number: 10504578
    Abstract: A volatile memory device includes a memory array of volatile charge storage cells, a counter to track a time since the volatile memory device has received a read/write command and a control element to automatically change the volatile memory device to a lower power state based on the time tracked by the counter.
    Type: Grant
    Filed: October 25, 2015
    Date of Patent: December 10, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Reza M Bacchus, Melvin K Benedict, Eric L Pope
  • High reliability OTP memory by using of voltage isolation in series
    Patent number: 10504908
    Abstract: A high-reliability one-time programmable memory adopting series high voltage partition, which relates to integrated circuit technology and comprises a first MOS tube, a second MOS tube and an anti-fuse element, wherein a gate end of the first MOS tube is connected to a second connecting line (WS), a first connecting end of the first MOS tube is connected to a gate end of the second MOS tube and a voltage limiting device, and a second connecting end of the first MOS tube is connected to a third connecting line (BL); a first connecting end of the second MOS tube is connected to a fourth connecting line (BR), a second connecting end of the second MOS tube is connected to the third connecting line (BL), and a gate end of the second MOS tube is connected to the voltage limiting device and the second connecting end of the first MOS tube.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: December 10, 2019
    Assignee: SICHUAN KILOWAY ELECTRONICS INC.
    Inventors: Jack Z. Peng, Junhua Mao, Xuyang Liao
  • Target row generator, DRAM, and method for determining a target row
    Patent number: 10497426
    Abstract: The present disclosure provides a target row generator. The target row generator includes a plurality of counting modules, a comparing module and a first processing module. Each of the plurality of counting modules is configured to generate a counting record, and includes a reset timer. The reset timer is configured to generate a reset signal to reset a corresponding one of the plurality of counting modules. The comparing module is connected to the plurality of counting modules and is configured to compare a plurality of counting records generated by the plurality of counting modules. The first processing module is connected to the comparing module and is configured to generate a target row record based on a comparison result from the comparing module. The quantity of the plurality of counting records is less than the quantity of the plurality of stressed rows.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: December 3, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Nung Yen, Po-Hsun Chang
  • Resistance change memory device
    Patent number: 10490271
    Abstract: According to one embodiment, a resistance change memory device comprises a memory cell array in which a plurality of resistance change storage elements each to store one of multiple resistance states as data represented in two or more bits are arranged, and a read unit to read the data of a selected one of the storage elements. In reading the data of the storage element, the read unit, selecting one at a time, applies multiple types of constant voltages to the storage element.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: November 26, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Ryu Ogiwara, Daisaburo Takashima
  • Methods for performing multiple memory operations in response to a single command and memory devices and systems employing the same
    Patent number: 10489316
    Abstract: Memory devices, memory systems, and methods of operating memory devices and systems are disclosed in which a single command can trigger a memory device to perform multiple operations, such as a single refresh command that triggers the memory device to both perform a refresh command and to perform a mode register read. One such memory device comprises a memory, a mode register, and circuitry configured, in response to receiving a command to perform a refresh operation at the memory, to perform the refresh operation at the memory, and to perform a read of the mode register. The memory can be a first memory portion, the memory device can comprise a second memory portion, and the circuitry can be further configured, in response to the command, to provide on-die termination at the second memory portion of the memory system during at least a portion of the read of the mode register.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: November 26, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Matthew A. Prather, Frank F. Ross, Randall J. Rooney
  • Device and method for data-writing
    Patent number: 10490233
    Abstract: A device includes a circuit cell, a voltage regulator, a first switching unit, a second switching unit, and a third switching unit. The voltage regulator is configured to output a write voltage. The first switching unit is configured to generate, in response to a control voltage, a current represented by an auxiliary signal. The second switching unit is configured to receive the auxiliary signal, and to turn on to transmit the auxiliary signal to the circuit cell. The third switching unit is configured to receive the write voltage, and to turn on to transmit the write voltage to the circuit cell.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: November 26, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Hao Lee, Yi-Chun Shih
  • Voltage reference computations for memory decision feedback equalizers
    Patent number: 10482932
    Abstract: A device includes a combinational circuit configured to create a one or more distortion correction factors used offset inter-symbol interference from a data stream on a distorted bit. The device also includes a selection circuit coupled to the combinational circuit. The selection circuit includes a feedback pin configured to receive a control signal and an output, wherein the selection circuit is configured to select a first distortion correction factor of the one or more distortion correction factors based upon the control signal and transmit the first distortion correction factor from the output.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: November 19, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Jennifer E. Taylor, Raghukiran Sreeramaneni
  • Ramp down sensing between program voltage and verify voltage in memory device
    Patent number: 10482984
    Abstract: Apparatuses and techniques are described for optimizing a program operation in a memory device. A storage location stores programing data for each word line, such as a program voltage for a set of memory cells. The set of memory cells may be periodically evaluated to determine updated programming setting(s). In one approach, the evaluation involves repeatedly sensing the set of memory cells between a program pulse and a verify signal in a program loop. The word line voltage can be stepped down to an intermediate voltage, then ramped down at a controlled rate while repeatedly sensing the memory cells, such as to detect an upper or lower tail of a threshold voltage distribution. The position of the tail can indicate a degree of over programming and this information can be used to adjust the programming setting(s) in a subsequent program operation.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: November 19, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Xiang Yang, Huai-Yuan Tseng, Deepanshu Dutta
  • Semiconductor memory device
    Patent number: 10482977
    Abstract: A semiconductor memory device includes a first transistor including a first end connected to a first pad and a second end connected to a first node, a second transistor including a first end connected to a second pad and a second end connected to the first node, a third transistor including a first end connected to the second pad, a second end connected to the first node, and a gate connected to a second node and having a size different from that of the second transistor, a fourth transistor including a first end connected to the first pad, a second end connected to the second node, and a gate connected to the first node, and a fifth transistor including a first end connected to the second pad, a second end connected to the second node, and a gate connected to the first node.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: November 19, 2019
    Assignee: TOSHIBA MEMEORY CORPORATION
    Inventors: Kei Shiraishi, Masaru Koyanagi, Mikihiko Ito, Yasuhiro Hirashima
  • Circuit and method for read latency control
    Patent number: 10475492
    Abstract: A memory device comprises an array of memory cells, and a plurality of sense amplifiers coupled with the memory cells. A controller is configured to execute a read operation in response to a command and address, including a read cycle in which the memory cells at the address are electrically coupled to the sense amplifiers, and in which the memory cells at the address are electrically decoupled from the sense amplifiers in response to a timing signal.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: November 12, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Shang-Chi Yang, Chun-Yu Liao, Yi-Wei Chang
  • Memory architecture having first and second voltages
    Patent number: 10468075
    Abstract: A memory macro includes: word lines; memory cells arranged in an array of columns and rows, the rows corresponding to the word lines; and switching circuits corresponding to the columns, each switching circuit being configured to selectively provide a first voltage value of a first voltage source or a different second voltage value of a second voltage source to corresponding voltage supply nodes of the columns; and wherein the word lines are configured to receive the second voltage value as a high logical value of the word lines; a selected one or more of the word lines is activated during a write operation, thereby defining an elapse of the write operation; and each switching circuit is further configured to selectively provide the corresponding first voltage value or the second voltage value substantially for an entirety of the write operation.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: November 5, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Atul Katoch, Cormac Michael O'Connell
  • Detecting method for a resistive random access memory cell
    Patent number: 10468100
    Abstract: The disclosure provides a detecting method for a resistive random access memory (RRAM) cell. The method includes: retrieving an RRAM cell and measuring a cell current of the RRAM cell; when a current value of the cell current is higher than a first threshold, performing at least one of a plurality of reset operations and a set operation to the RRAM cell and determining whether a resistance state of the RRAM cell has been switched after experiencing the at least one of the reset operations and the set operation. If no, a recovery operation is performed to the RRAM cell to recover the RRAM cell; if yes, the RRAM is determined to be in a healthy state.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: November 5, 2019
    Assignee: Winbond Electronics Corp.
    Inventors: Lih-Wei Lin, Yu-An Chen, Guan-Yi Li, Hsuan-Pao Tseng
  • Memory module voltage regulator module (VRM)
    Patent number: 10453516
    Abstract: An example device in accordance with an aspect of the present disclosure includes a memory module having a voltage regulator module (VRM) to receive input power and deliver output power to components of the memory module at a first power plane. A sufficient number of stitching capacitors are to couple the first power plane to a second power plane.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: October 22, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Reza M Bacchus, Melvin K Benedict, Stephen F Contreras, Eric L Pope, Chi K Sides, Chun-Pin Huang
  • In-channel memory mirroring
    Patent number: 10452470
    Abstract: Embodiments of the present invention provide methods, program products, and systems for improving DIMM level memory mirroring. Embodiments of the present invention can be used to configure a first memory module device of a pair memory module devices to receive a set of read and write operations and configure a second memory module device of the pair of memory module devices to receive only write operations of the set of read and write operations. Embodiments of the present invention can, responsive to detecting a failure, reconfiguring the first and the second memory module device to set the first memory module device to receive only write operations of the set of read and write operations and the second memory module device to receive read and write operations of the set of read and write operations.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: October 22, 2019
    Assignee: International Business Machines Corporation
    Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Saravanan Sethuraman
  • Multi-phase clock division
    Patent number: 10438651
    Abstract: Devices and methods include receiving write command at a command interface of the semiconductor device to write data to memory. An external data strobe is received at a data strobe pin of the semiconductor device. The received external data strobe is divided into multiple phases using phase division circuitry to divide the data strobe into multiple phases to be used in writing the data to the memory.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: October 8, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Daniel B. Penney