Abstract: A semiconductor device includes an antenna functioning as a coil, a capacitor electrically connected to the antenna in parallel, a passive element forming a resonance circuit with the antenna and the capacitor by being electrically connected to the antenna and the capacitor in parallel, a first field effect transistor controlling whether the passive element is electrically connected to the antenna and the capacitor in parallel or not, and a memory circuit. The memory circuit includes a second field effect transistor which includes an oxide semiconductor layer where a channel is formed and in which a data signal is input to one of a source and a drain. The gate voltage of the first field effect transistor is set depending on the voltage of the other of the source and the drain of the second field effect transistor.

Abstract: In an apparatus for producing thin layers on substrates for solar cell production, wherein the thin layers are applied by an APCVD process at temperatures of more than 250° C., the substrates are conveyed on a horizontal conveyor path and coated by means of an APCVD coating in continuous operation. The conveyor path has conveyor rollers, which consist of a temperature-resistant, non-metallic material, preferably of ceramic. A heating device and/or a purge gas feeding device is/are arranged on that side of the conveyor path which is remote from the coating apparatus.

Abstract: A plasma processing apparatus is provided that converts a gas into plasma using a high frequency power and performs a plasma process on a workpiece using an action of the plasma. The plasma processing apparatus includes a processing chamber that can be depressurized, a mounting table that is arranged within the processing chamber and holds the workpiece, an electrostatic chuck that is arranged on the mounting table and electrostatically attracts the workpiece by applying a voltage to a chuck electrode, a heater arranged within or near the electrostatic chuck, and a temperature control unit. The heater is divided into a circular center zone, at least two middle zones arranged concentrically at an outer periphery side of the center zone, and an edge zone arranged concentrically at an outermost periphery. The temperature control unit adjusts a control temperature of the heater with respect to each of the zones.

Abstract: A substrate is patterned to form trenches and a semiconductor fin between the trenches. Insulators are formed in the trenches and a first dielectric layer is formed to cover the semiconductor fin and the insulators. A dummy gate strip is formed on the first dielectric layer. Spacers are formed on sidewalls of the dummy gate strip. The dummy gate strip and the first dielectric layer underneath are removed until sidewalls of the spacers, a portion of the semiconductor fin and portions of the insulators are exposed. A second dielectric layer is selectively formed to cover the exposed portion of the semiconductor fin, wherein a thickness of the first dielectric layer is smaller than a thickness of the second dielectric layer. A gate is formed between the spacers to cover the second dielectric layer, the sidewalls of the spacers and the exposed portions of the insulators.

Abstract: An organic EL display panel in which pixels are arranged in a matrix, including: light-emitting layers disposed above pixel electrode layers in intervals between adjacent ones of column banks; an opposing electrode layer disposed above the light-emitting layers, the opposing electrode layer including a light-transmissive material; column light-shielding layers disposed higher than the pixel electrode layers, extending in the column direction, arranged side-by-side in the row direction, and overlapping row-direction edge portions of the pixel electrode layers in plan view of a substrate; and row light-shielding layers disposed higher than the pixel electrode layers, extending in the row direction, arranged side-by-side in the column direction, overlapping column-direction edge portions of the pixel electrode layers and partially overlapping contact regions in plan view of the substrate.

Abstract: This disclosure relates to a plasma processing system for controlling plasma density near the edge or perimeter of a substrate that is being processed. The plasma processing system may include a plasma chamber that can receive and process the substrate using plasma for etching the substrate, doping the substrate, or depositing a film on the substrate. This disclosure relates to a plasma processing system that may include a power electrode that may be opposite a bias electrode and a focus ring electrode that surrounds the substrate. In one embodiment, the power electrode may be coupled to a direct current (DC) source. Power applied to the bias electrode may be used to draw ions to the substrate. The plasma density may be made more uniform by applying a focus ring voltage to the focus ring that is disposed around the substrate and/or the bias electrode.

Abstract: A method of forming a memory device that in one embodiment may include forming a magnetic tunnel junction on a first electrode using an electrically conductive mask and subtractive etch method. Following formation of the magnetic tunnel junction, at least one dielectric layer is deposited to encapsulate the magnetic tunnel junction. Ion beam etching/Ion beam milling may then remove the portion of the at least one dielectric layer that is present on the electrically conductive mask, wherein a remaining portion of the at least one dielectric layer is present over the first electrode. A second electrode may then be formed in contact with the electrically conductive mask.

Abstract: A step for forming an island-shaped semiconductor layer of a semiconductor device used in a display device is omitted in order to manufacture the semiconductor device with high productivity and low cost. The semiconductor device is manufactured through four photolithography processes: four steps for forming a gate electrode, for forming a source electrode and a drain electrode, for forming a contact hole, and for forming a pixel electrode. In the step for forming the contact hole, a groove portion in which a semiconductor layer is removed is formed, whereby formation of a parasitic transistor is prevented. An oxide semiconductor is used as a material of the semiconductor layer in which a channel is formed, and an oxide semiconductor having a higher insulating property than the semiconductor layer is provided over the semiconductor layer.

Abstract: A three-dimensional memory device including self-aligned drain select level electrodes is provided. Memory stack structures extend through an alternating stack of insulating layers and spacer material layers. Each of the memory stack structures includes a memory film and a memory level channel portion. Drain select level channel portions are formed over the memory level channel portions with respective lateral shifts with respect to underlying memory stack structures. The direction of lateral shifts alternates from row to row for each row of drain select level channel portions. Drain select level gate dielectrics and drain select level gate electrodes are formed on the drain select level channel portions. Each drain select level gate electrode controls two rows of drain select level channel portions, and is laterally spaced from neighboring drain select level gate electrodes.

Abstract: A chip package includes a chip, a dam layer, a carrier substrate and a light shielding passivation layer. The chip has a first surface and a second surface opposite to the first surface, and a side surface is disposed between the first surface and the second surface. The dam layer is disposed on the first surface, and the carrier substrate is disposed on the dam layer. The light shielding passivation layer is disposed under the second surface and extended into the carrier substrate to cover the side surface of the chip.

Abstract: A quantum computing system includes a quantum circuit device, a substrate having a first surface on which the quantum processing device is disposed, and one or more vias each extending through the substrate. The vias include a material that is a superconducting material during operation of the quantum computing system.

Abstract: A system and method for providing support to semiconductor wafer is provided. An embodiment comprises introducing a vacancy enhancing material during the formation of a semiconductor ingot prior to the semiconductor wafer being separated from the semiconductor ingot. The vacancy enhancing material forms vacancies at a high density within the semiconductor ingot, and the vacancies form bulk micro defects within the semiconductor wafer during high temperature processes such as annealing. These bulk micro defects help to provide support and strengthen the semiconductor wafer during subsequent processing and helps to reduce or eliminate a fingerprint overlay that may otherwise occur.

Abstract: FinFET devices and methods of forming the same are disclosed. One of the FinFET devices includes a substrate, multiple gates and a single spacer wall. The substrate is provided with multiple fins extending in a first direction. The multiple gates extending in a second direction different from the first direction are provided respectively across the fins. Two of the adjacent gates are arranged end to end. The single spacer wall extending in the first direction is located between the facing ends of the adjacent gates and is in physical contact with a gate dielectric material of each of the adjacent gates.

Abstract: The semiconductor device comprises a semiconductor substrate (1), a sensor or sensor array (2) arranged at a main surface (10) of the substrate, an integrated circuit (3) arranged at or above the main surface, and a focusing element (17) comprising recesses (4) formed within a further main surface (11) of the substrate opposite the main surface. The focusing element may be arranged opposite the sensor or sensor array (2), which may be a photosensor or photodetector or an array of photosensors or photodetectors, for instance. The focusing element (17) is formed by etching the recesses (4) into the semiconductor material.

Abstract: An electronic component housing package includes a substrate having an upper surface including a mount region on which an electronic component is to be mounted; a frame body disposed on the upper surface of the substrate, the frame body being provided with a through-hole portion; and an input/output member disposed on the frame body so as to block the through-hole portion, the input/output member having wiring conductors which are to be electrically connected to the electronic component, the wiring conductors extending to an inside and outside of the frame body and also extending along a lower surface of the input/output member on the outside of the frame body. The input/output member is provided with a cutout portion which is cut out so as to extend from a gap between the wiring conductors on the lower surface along the wiring conductors to an outer side surface of the input/output member.

Abstract: A semiconductor includes a first transistor and a second transistor. The first transistor includes a first and a second epitaxial layer, formed of a first semiconductor material. The second epitaxial layer is disposed over the first epitaxial layer. The first transistor also includes a first gate dielectric layer surrounds the first and second epitaxial layers and extends from a top surface of the first epitaxial layer to a bottom surface of the second epitaxial layer and a first metal gate layer surrounding the first gate dielectric layer. The second transistor includes a third epitaxial layer formed of the first semiconductor material and a fourth epitaxial layer disposed directly on the third epitaxial layer and formed of a second semiconductor. The second transistor also includes a second gate dielectric layer disposed over the third and fourth epitaxial layers and a second metal gate layer disposed over the second gate dielectric layer.

Abstract: A spin control mechanism includes a spin portion and a first channel portion. The spin portion has a magnetic moment that can be reversed and rotated. The first channel portion is provided in contact with the spin portion, and is configured from ferromagnetic insulator. Then, the spin control mechanism controls a direction of the magnetic moment of the spin portion using a spin current generated by a temperature gradient provided to the first channel portion.

Abstract: Described is an apparatus which comprises: first, second, and third free magnetic layers; a first metal layer of first material coupled to the first and third free magnetic layers; and a second metal layer of second material different from the first material, the second metal layer coupled to the second and third free magnetic layers. Described is an STT majority gate device which comprises: a free magnetic layer in a ring; and first, second, third, and fourth free magnetic layers coupled to the free magnetic layer.

Abstract: Sacrificial gate structures having an aspect ratio of greater than 5:1 are formed on a substrate. In some embodiments, each sacrificial gate structure straddles a portion of a semiconductor fin that is present on the substrate. An anchoring element is formed orthogonal to each sacrificial gate structure rendering the sacrificial gate structures mechanically stable. After formation of a planarization dielectric layer, each anchoring element can be removed and thereafter each sacrificial gate structure can be replaced with a functional gate structure.

Abstract: A GaN transistor with polysilicon layers for creating additional components for an integrated circuit and a method for manufacturing the same. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer.