Abstract: A quantum computing apparatus, including a quantum circuit device; and an interposer including a connectorization layer including a plurality of terminals for connecting the quantum computing apparatus to a corresponding plurality of cables and a plurality of signal lines electrically coupled, via electrical contacts, to the plurality of terminals; and at least one intermediate layer between the quantum circuit device and the connectorization layer, the at least one intermediate layer comprising an integrated circuit layer, the at least one intermediate layer being electrically coupled to the signal lines of the interposer. The interposer is configured to supply the quantum circuit device, during operation of the quantum computing apparatus, at least control signals and readout signals to and from the plurality of cables.

Abstract: A display device including a plurality of semiconductor light emitting devices, each corresponding semiconductor light emitting device having a first conductive electrode, a second conductive electrode and a light-emitting surface configured to emit light; a first wiring line electrically connected to the first conductive electrode; and a second wiring line disposed to cross the first conductive electrode, and be electrically connected to the second conductive electrode. Further, the second wiring line is formed to surround a periphery of the light-emitting surface of the semiconductor light emitting devices to reflect light emitted by the light emitting devices toward a front surface of the display device.

Abstract: A bank repair method for repairing a defect portion of a bank in a process of manufacturing an organic electroluminescence (EL) display device including a substrate, banks formed over the substrate, and light-emitting layers formed in concave spaces defined by the banks. The bank repair method includes: examining whether or not a bank having a defect portion is present; and when a bank having a defect portion is present, repairing the bank by applying a repair material containing a gas adsorbent to the defect portion and curing the repair material; and after curing the repair material, baking the repair material by irradiating the repair material with infrared laser light.

Abstract: A method of fabricating raised fin structures is provided, the fabricating including: providing a substrate and at least one dielectric layer over the substrate; forming a trench in the at least one dielectric layer, the trench having a lower portion, a lateral portion, and an upper portion, the upper portion being at least partially laterally offset from the lower portion and being joined to the lower portion by the lateral portion; and, growing a material in the trench to form the raised fin structure, wherein the trench is formed to ensure that any growth defect in the lower portion of the trench terminates either in the lower portion or the lateral portion of the trench and does not extend into the upper portion of the trench.

Abstract: A method of manufacturing a light emitting device includes providing a wafer having a substrate and a plurality of semiconductor stacked-layer bodies stacked on the substrate, an upper surface of the substrate being exposed at an outer peripheral region of each of the plurality of semiconductor stack bodies in a plan view, forming a separation layer integrally covering the upper surface of the substrate and an upper surface of the semiconductor stacked-layer body, the separation layer including a separation boundary, forming a support member on the separation layer, removing the substrate, forming a wavelength conversion layer on a side of the semiconductor stack body and the separation layer where the substrate is removed, the wavelength conversion layer made of a resin containing a wavelength conversion member, and removing the wavelength conversion layer located in the outer peripheral region by separating the separation layer at the separation boundary.

Abstract: A display device including a substrate; a first electrode on the substrate; and a plurality of semiconductor light emitting devices disposed on the first electrode; and a second electrode. Further, at least one of the semiconductor light emitting devices includes a first conductive semiconductor layer; a second conductive semiconductor layer overlapping with the first conductive semiconductor layer; and an active layer between the first conductive semiconductor layer and the second conductive semiconductor layer. In addition, an upper surface of the second conductive layer includes a recess groove having a bottom portion and a lateral wall portion formed along an edge of the second conductive semiconductor layer, and the second electrode extends partially on the bottom portion of the groove and on the lateral wall portion.

Abstract: Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes through-vias, an integrated circuit die mounting region, and a material disposed around and between the through-vias and the integrated circuit die mounting region. An interconnect structure is disposed over the material, the through-vias, and the integrated circuit die mounting region. The interconnect structure includes a dummy feature disposed proximate one of the through-vias.

Abstract: A substrate processing apparatus is disclosed. The substrate processing apparatus includes a process chamber configured to accommodate a substrate; a gas supply unit configured to supply a process gas into the process chamber; a lid member configured to block an end portion opening of the process chamber; an end portion heating unit installed around a side wall of an end portion of the process chamber; and a thermal conductor installed on a surface of the lid member in an inner side of the process chamber, and configured to be heated by the end portion heating unit.

Abstract: In one embodiment, a semiconductor package structure includes a substrate having a well region extending from a major surface. An interposer structure is attached to the substrate within the well region. The interposer structure has a major surface that is substantially co-planar with the major surface of the substrate. An electrical device is directly attached to the substrate and the interposer structure. The interposer structure can be an active device, such as a gate driver integrated circuit, or passive device structure, such as an impedance matching network.

Abstract: Magnet placement is described for integrated circuit packages. In one example, a terminal is applied to a magnet. The magnet is then placed on a top layer of a substrate with solder between the terminal and the top layer, and the solder is reflowed to attach the magnet to the substrate.

Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a package substrate having first and second major surfaces. The package substrate includes a base substrate having a mold material and a plurality of interconnect structures including via contacts extending through the first to the second major surface of the package substrate. A die having conductive contacts on its first or second surface is provided. The conductive contacts of the die are electrically coupled to the interconnect structures. A cap is formed over the package substrate to encapsulate the die.

Abstract: Disclosed is a film formation method, including vaporizing a plurality of raw material monomers in respective corresponding vaporizers, supplying the plurality of raw material monomers into a film formation apparatus, causing vapor deposition polymerization of the plurality of raw material monomers in the film formation apparatus to form an organic film on a substrate, and removing an impurity contained in at least one raw material monomer among the plurality of raw material monomers before the vapor deposition polymerization.

Abstract: Some embodiments of the present disclosure provide a method of manufacturing a device. The method includes providing a carrier, the carrier including a top surface, covering a portion of the top surface with a plurality of active dies, disposing a protrudent band over a periphery of the carrier, wherein the protrudent band includes a rim shaped along the contour of the carrier, and forming a molding compound over the carrier to cover the plurality of active dies. A method for determining a width of the protrudent band of a device described herein is also provided.

Abstract: An embodiment semiconductor device includes a substrate and a dielectric layer over the substrate. The dielectric layer includes a first conductive line and a second conductive line. The second conductive line comprises a different conductive material than the first conductive line.

Abstract: The present disclosure provides a method for forming a semiconductor device. The semiconductor device includes a first conductive line disposed over a substrate. The first conductive line is located in a first interconnect layer and extends along a first direction. The semiconductor device includes a second conductive line and a third conductive line each extending along a second direction different from the first direction. The second and third conductive lines are located in a second interconnect layer that is different from the first interconnect layer. The second and third conductive lines are separated by a gap that is located over or below the first conductive line. The semiconductor device includes a fourth conductive line electrically coupling the second and third conductive lines together. The fourth conductive line is located in a third interconnect layer that is different from the first interconnect layer and the second interconnect layer.

Abstract: In one embodiment of the present invention, an electronic device includes a first emitter/collector region and a second emitter/collector region disposed in a substrate. The first emitter/collector region has a first edge/tip, and the second emitter/collector region has a second edge/tip. A gap separates the first edge/tip from the second edge/tip. The first emitter/collector region, the second emitter/collector region, and the gap form a field emission device.

Abstract: A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate having a source region and a drain region. Further, the semiconductor structure includes a floating gate, a word line, and an erase gate spaced over the semiconductor substrate between the source and drain regions with the floating gate arranged between the word line and the erase gate. The semiconductor structure further includes a first dielectric sidewall region disposed between the word line and the floating gate, as well as a second dielectric sidewall region disposed between the erase and floating gates. A thickness of the first dielectric sidewall region is greater than a thickness of the second dielectric sidewall region. A method of manufacturing the semiconductor structure and an integrated circuit including the semiconductor structure are also provided.

Abstract: Sacrificial gate structures having an aspect ratio of greater than 5:1 are formed on a substrate. In some embodiments, each sacrificial gate structure straddles a portion of a semiconductor fin that is present on the substrate. An anchoring element is formed orthogonal to each sacrificial gate structure rendering the sacrificial gate structures mechanically stable. After formation of a planarization dielectric layer, each anchoring element can be removed and thereafter each sacrificial gate structure can be replaced with a functional gate structure.

Abstract: A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A plurality of gate formation layers is formed on an etch stop layer disposed on the fin. The plurality of gate formation layers include a dummy gate layer formed from a dielectric material. The plurality of gate formation layers is patterned to form a plurality of dummy gate elements on the etch stop layer. Each dummy gate element is formed from the dielectric material. A spacer layer formed on the dummy gate elements is etched to form a spacer on each sidewall of dummy gate elements. A portion of the etch stop layer located between each dummy gate element is etched to expose a portion the semiconductor fin. A semiconductor material is epitaxially grown from the exposed portion of the semiconductor fin to form source/drain regions.

Abstract: Provided is a thin film transistor array panel. The thin film transistor array panel includes: an insulation substrate including a display area with a plurality of pixels and a peripheral area around the display area; a gate line and a data line positioned in the display area of the insulation substrate; a first driving signal transfer line and a second driving signal transfer line positioned in the peripheral area of the insulation substrate; a first insulating layer positioned on the gate line and the data line; and a first photosensitive film positioned on the first driving signal transfer line and the second driving signal transfer line, in which the first photosensitive film is disposed only in the peripheral area.