Patents Examined by Stanley D. Miller, Jr.
  • Patent number: 4359648
    Abstract: A first diode having a polarity opposite to the diode characteristic between the emitter and base electrodes is connected across these electrodes of a first transistor, a resistor having a high resistance is connected between the collector and the base electrodes of the first transistor and a first source of high reference potential is connected to the collector electrode. The collector electrode of a second transistor is connected to the base electrode of the first transistor and to a second diode and the emitter electrode of the second transistor is connected to a second source of low reference potential.
    Type: Grant
    Filed: September 19, 1978
    Date of Patent: November 16, 1982
    Assignee: Nippon Electric Co., Ltd.
    Inventors: Hiroshi Hada, Tsutomu Hirayama
  • Patent number: 4355243
    Abstract: In the disclosed device, a square wave generator drives a network composed of a parallel resonant circuit in series with a series resonant circuit. The resonant frequency of the parallel resonant circuit is substantially equal to the fundamental frequency of the square wave voltage generator and lower than the resonant frequency of the series resonant circuit. The resonant frequency of the series resonant circuit is lower than the frequency of the third harmonic of the square wave voltage generator. A load coupleable to the parallel resonant circuit has a complex impedance which shifts the current at the fundamental frequency about 30.degree. relative to the fundamental square wave voltage.
    Type: Grant
    Filed: January 2, 1980
    Date of Patent: October 19, 1982
    Assignee: Sachs-Systemtechnik GmbH
    Inventor: Rudy Tellert
  • Patent number: 4353000
    Abstract: An electronic divider circuit for processing first and second electrical signals A and B. The second electrical signal B is divided by the first electrical signal A, thereby producing a third electrical signal B/A. This divider circuit is configured very easily by a combination of differential amplifiers and is suitable for construction with integrated circuits.
    Type: Grant
    Filed: June 18, 1979
    Date of Patent: October 5, 1982
    Assignee: Hitachi, Ltd.
    Inventor: Masaru Noda
  • Patent number: 4352029
    Abstract: Signal processing circuitry, preferably for use in multiplying two input signals, one at RF frequency and one at base-band frequency, which includes a pair of PIN diodes connected in a generally symmetrical circuit configuration using a single bias supply and including a trimming resistor for controlling the current through a selected one of the diodes so that the characteristics of both diodes can be matched over substantially the complete range of control current values therefor. Further, the circuit configuration permits the use of an easy and effective technique for compensating for temperature changes of the circuit during operation.
    Type: Grant
    Filed: December 13, 1979
    Date of Patent: September 28, 1982
    Assignee: Signatron, Inc.
    Inventors: Paul F. Mahoney, Jerrold L. Bonn
  • Patent number: 4352069
    Abstract: An electronic filter circuit is described having first and second selective circuits each of said selective circuits having an input terminal for receiving an input voltage, each of said selection circuits comprising a first capacitor, an integrator means providing an output signal, switching means for connecting said capacitor alternatively between said input terminal and said integrator output, respectively between a common input-output terminal and said integrator input, in response to a switching signal, further comprising means for providing first and second switching signals to said first and second selection circuits, said signals having the same frequency but differing in phase whereby each of said first and second selective circuits provides for alterate sampling of an input signal and means for combining said integrator means output signals.
    Type: Grant
    Filed: December 17, 1979
    Date of Patent: September 28, 1982
    Assignee: Centre Electronique Horloger S.A.
    Inventor: Roger Dessoulavy
  • Patent number: 4350904
    Abstract: An integrated circuit current source (10) has first (16) and second (30) current mirrors regeneratively coupled. The transistors (32, 34) of the second mirror (30) have unequal current densities, so that a resistor (40) connected to the emitter of the lower current density transistor (34) establishes a temperature-dependent output current. One of the transistors (18, 20, 34) has its base and emitter connected together through a modifying resistor (42, 53, 55) to modify the temperature dependence of the output. In one embodiment (10), the modifying resistor (42) connects the base and emitter of the lower current density transistor (34) and increases the temperature dependence of the output to make it directly proportional to the absolute temperature. Other embodiments (52, 54) are disclosed for obtaining both zero and negative temperature coefficient values for the output.
    Type: Grant
    Filed: September 22, 1980
    Date of Patent: September 21, 1982
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventor: Robert R. Cordell
  • Patent number: 4350903
    Abstract: The specification discloses an electronic switch for operating an incandescent lamp from a plurality of stations. A plurality of normally closed mechanical switches may be wired in series with the lamp, and electronic switch to form a single series circuit. Actuation of any single mechanical switch interrupts the power, causing the electronic switch to change its state. Additional circuitry for dimming and state preservation in the event of a complete power failure are also disclosed. The rate at which power is applied or reduced may be varied in accordance with circuit values.
    Type: Grant
    Filed: April 27, 1979
    Date of Patent: September 21, 1982
    Inventors: Bruce D. Jimerson, Henry H. Nakasone
  • Patent number: 4349750
    Abstract: A switching circuit in which one out of a plurality of input channels is connectable to an output channel via one of the switching devices in the circuit. Each of the switching devices comprises an emitter-coupled pair of transistors which have a switchable current source in the emitter lead, the base of the first and the second transistor, respectively, of each pair being connected to one of the inputs and to the output, respectively. The output channel of the circuit comprises a transistor the emitter of which is connected to the output and the base to the interconnected collectors of the second transistors, this junction point being connected to a voltage-carrying terminal via a resistor. Via a selection switch which is connected to the switchable current sources only one of the input channels can at all times be connected through to the output channel.
    Type: Grant
    Filed: January 14, 1980
    Date of Patent: September 14, 1982
    Assignee: U.S. Philips Corporation
    Inventor: Martinus F. A. M. Geurts
  • Patent number: 4349755
    Abstract: A circuit for detecting when the product of two independent currents equals or exceeds a predetermined upper limit is disclosed. The circuit includes a load current source for providing a load current for defining the predetermined upper limit; a differential amplifier including first and second transistors having their emitters connected in common to an emitter current source, wherein the collector of the first transistor is connected to the load current source for providing an output signal at the collector that changes state when the collector current is not less than the load current; a first combination of components for providing a voltage signal at the base of the first transistor that is representative of the natural logarithm of the reciprocal of a first independent current; and a second combination of components for providing a voltage signal at the base of the second transistor that is representative of the natural logarithm of a second independent current.
    Type: Grant
    Filed: February 11, 1980
    Date of Patent: September 14, 1982
    Assignee: National Semiconductor Corporation
    Inventor: Edward C. Bee
  • Patent number: 4349752
    Abstract: The present invention teaches a magnetically coupled drive circuit for coupling isolated power switching transistors to low power dissipative control circuitry. Drive energy stored in the magnetic transformer is controllably varied between preselected minimum "turn-on" and dissipative maximum levels to concurrently insure turn-on/turn-off capability and minimize quiescent, steady state dissipation.
    Type: Grant
    Filed: July 28, 1980
    Date of Patent: September 14, 1982
    Assignee: Reliance Electric Company
    Inventor: Luciano Forte
  • Patent number: 4348598
    Abstract: A switching circuit for conducting a pulse of current between a first and a second terminal, the circuit including a transistor having a base connected to the first terminal, an emitter and a collector and a saturable-core transformer having an emitter winding coupling the emitter to the first terminal and a collector winding coupling the second terminal to the collector so as to provide regenerative current feedback rapidly driving the transistor into saturation after the transistor is suitably triggered, the circuit diverting the collector current from the emitter to the base circuit sweeping carriers out of the base and hastening the transistor turn-off after the transformer core saturates decoupling the emitter and collector windings.
    Type: Grant
    Filed: January 25, 1980
    Date of Patent: September 7, 1982
    Inventor: Steve Smith
  • Patent number: 4348596
    Abstract: The circuit compensates for the difference in the source impedances of signal and reference generating circuits whose outputs are coupled to a sense circuit which loads (draws current from) the signal and reference generating circuits. The signal generating circuit has a source impedance (R.sub.1) and produces either one of two (V.sub.1H or V.sub.1L) output signal levels which is coupled via a first transmission gate having an "ON" impedance R.sub.2 to a first input terminal of the sense circuit. The reference generating circuit has a lower source impedance (R.sub.3) than the signal source and produces an output intermediate the two signal levels which is coupled via a second transmission gate having an "ON" impedance R.sub.4 to a second input terminal of the sense circuit. The reference voltage applied to the second input of the sense circuit is maintained at a predetermined level between the high and low levels of the signal applied to the first input of the sense circuit, by making the sum of R.sub.
    Type: Grant
    Filed: December 27, 1979
    Date of Patent: September 7, 1982
    Assignee: RCA Corporation
    Inventors: James H. Atherton, Clifford P. Jindra
  • Patent number: 4347445
    Abstract: A high-current VMOS transistor having a source connected to a floating reference voltage terminal is switched between conducting and non-conducting states by a low power source including complementary-symmetry FET's. When the VMOS is back biased a low impedance path having a constant predetermined voltage exits between the VMOS source and drain via one of the bipolar transistors. This prevents false triggering of the VMOS if the reference voltage drops below a nominal value. A diode polarized to pass current oppositely from the source drain path and in shunt with the source drain path prevents the VMOS from conducting if the reference voltage rises above the nominal value. The bipolar transistors are shunted by a zener diode to maintain a predetermined voltage across the bipolar transistors, i.e. between the reference voltage terminal and a terminal connected through a load resistor to a power supply terminal.
    Type: Grant
    Filed: December 31, 1979
    Date of Patent: August 31, 1982
    Assignee: Exxon Research and Engineering Co.
    Inventor: Richard H. Baker
  • Patent number: 4345164
    Abstract: A transistor switching circuit is disclosed employing complimentary switching transistors which selectively connect either of two voltages to an output which is common to both switching transistors. Each of the switching transistors is driven by a constant current source. A diode is provided between a base and a collector of each of the switching transistors and the diode is positioned such that its polarity corresponds to the polarity of the base-collector junction of the respective switching transistor. A variable resistor may also be provided between the commonly connected bases and emitters of the switching transistors. Furthermore, the bases of the switching transistors may be coupled to the resistance by further diodes and each constant current source may also include a further transistor whose collector output connects to the input of the other current source.
    Type: Grant
    Filed: November 16, 1979
    Date of Patent: August 17, 1982
    Assignee: Siemens Aktiengesellschaft
    Inventor: Johannes Gies
  • Patent number: 4342925
    Abstract: A circuit arrangement for interruptionless switching to the higher of two feed voltages in a buffered current supply. Each of the feed voltages is applied to the base of a driving transistor, via a diode, and to the emitter of a complementary switching transistor. The emitters of both driving transistors are connected to reference potential via a common resistor. The collector of each driving transistor is connected to the base of the respective switching transistor and the collectors of both switching transistors are connected to the output terminal. Switching to the higher of the two applied voltages is automatic and instantaneous.
    Type: Grant
    Filed: June 30, 1980
    Date of Patent: August 3, 1982
    Assignee: Siemens Aktiengesellschaft
    Inventor: Ludwig Schick
  • Patent number: 4341962
    Abstract: An electronic gain control device including a first bipolar circuit having log transfer functional elements, preferably in the form of a pair of parallel first transistors of different polarities, and a second bipolar circuit including antilog transfer function elements, preferably a pair of second transistors connected in parallel and of opposite polarity. A gain control signal is summed with the log output signal of the first bipolar circuit to produce a second output signal antilogarithmically related to the first output signal and the gain control signal.The log and antilog transfer functional elements receive a bias signal of sufficient magnitude relative to the input signal that the entire circuit is in continuous electrical conduction in order to operate in a class A domain.
    Type: Grant
    Filed: June 3, 1980
    Date of Patent: July 27, 1982
    Assignee: Valley People, Inc.
    Inventor: Paul C. Buff
  • Patent number: 4339723
    Abstract: A pulse width discriminator using a negative logic technique including two monostable multivibrators for generating test pulses and a D-latch for generating an output signal in response to the test pulses indicating that the received signal is of a predetermined length.
    Type: Grant
    Filed: January 24, 1980
    Date of Patent: July 13, 1982
    Assignee: The Bendix Corporation
    Inventor: Henry C. Yee
  • Patent number: 4339669
    Abstract: A circuit responsive to a supplied control input signal for alternately sourcing and sinking current at an output the values of which are accurately matched comprising a single current reference source and a single NPN current mirror circuit. The current reference source is unilaterally coupled to the output when the circuit is in a first mode of operation to provide the source current and is coupled to the NPN current mirror circuit which is rendered conductive in a second mode of operation to provide the input current to said current mirror. The output of the current mirror being coupled to the output sinks current thereat which is substantially equal to the input current supplied thereto. The NPN current mirrors comprises a pair of matched transistors having the bases and emitters interconnected at first and second nodes respectively.
    Type: Grant
    Filed: July 8, 1980
    Date of Patent: July 13, 1982
    Assignee: Motorola, Inc.
    Inventors: Robert B. Jarrett, James J. LoCascio
  • Patent number: 4339672
    Abstract: A delay circuit includes first and second MISFETs and a capacitance element connected to the common juncture of the first and the second MISFETs. The electricity of the capacitance element is charged through the first MISFET and is discharged through the second MISFET. Since the first and the second MISFETs effectively perform a push-pull operation, a signal of a predetermined level and a predetermined delay time to be delivered to a circuit having a logic threshold voltage is derived from the common juncture.
    Type: Grant
    Filed: July 12, 1979
    Date of Patent: July 13, 1982
    Assignee: Hitachi, Ltd.
    Inventor: Katsuyuki Sato
  • Patent number: 4338527
    Abstract: A voltage-current conversion circuit comprises an input terminal, a conversion terminal, an output terminal, first and second emitter-coupled transistors having their bases respectively connected to the input terminal receiving an input signal and the conversion terminal, a current mirror load circuit connected to collectors of the first and second transistors, a constant current source connected to emitters of the first and second transistors, and an output transistor having its base connected to the collector of the second transistor and its emitter to the conversion terminal. When the collector of the output transistor is connected to the output terminal and an impedance element is connected to the conversion terminal, a current is provided at the output and conversion terminals which is obtained by dividing an input signal voltage applied to the input terminal with an impedance value of the impedance element. The voltage-current conversion circuit serves as a negative current conveyor.
    Type: Grant
    Filed: June 11, 1980
    Date of Patent: July 6, 1982
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventor: Katsumi Nagano