Patents Examined by Stanley D. Miller
  • Patent number: 5166548
    Abstract: A Hall element switching system which provide clean switching and wherein the system operate and release points are the same. The system includes a Hall element, first and second comparator circuits and a feedback circuit. The Hall element is the sensing part of the system and produces a voltage output which is proportional to the strength of the magnetic field impinging thereon. The output of the Hall element controls the switching of the first and second comparator circuits. The second comparator circuit, in turn, controls the output of the feedback circuit. The feedback circuit output is connected to the input of the first comparator circuit and can be at one of three levels. The feedback circuit by being connected to the input of the first comparator circuit causes a shift in the operate and release points of the first comparator circuit. The output of the first comparator circuit is the system output.
    Type: Grant
    Filed: June 14, 1990
    Date of Patent: November 24, 1992
    Inventor: Richard W. Nelson
  • Patent number: 5164614
    Abstract: A bias voltahe generating circuit which is low in power consumption and small in chip size of an IC and does not pickup noises readily. The bias voltage generating circuit comprises a current mirror circuit including a diode-connected first transistor of a first conduction type and second and third transistors of the first conduction type, and bias voltage generating fourth and fifth transistors of a different second conduction type having input electrodes connected to output electrodes of the second and third transistors, respectively. The first to third transistors and the fourth and fifth transistors are formed on a single chip semiconductor substrate as a semiconductor integrated circuit. The bias voltage generating circuit further comprises a resistor provided outside the integrated circuit and connected to an input electrode of the first transistor, and a predetermined bias current is supplied to the first transistor through the resistor.
    Type: Grant
    Filed: July 10, 1991
    Date of Patent: November 17, 1992
    Assignee: Sony Corporation
    Inventor: Itaru Maekawa
  • Patent number: 5165076
    Abstract: A ferroelectric liquid crystal device comprises a pair of opposite electrodes and a ferroelectric liquid crystal disposed between the electrodes. At least one of the opposite electrodes is coated with a primer layer and an alignment layer on the primer layer. The alignment layer has a thickness d.sub.2 and is made of a material having a dielectric constant .epsilon..sub.2, and the primer layer has a thickness d.sub.1 and is made of a material having a dielectric constant .epsilon..sub.1 which are greater than d.sub.2 and .epsilon..sub.2, respectively. The ferroelectric liquid crystal is at least one mesomorphic compound represented by the formula R.sub.1 --A.sub.1 --X--A.sub.2 --R.sub.2 wherein A.sub.1 and A.sub.2 respectively denote a 6-membered ring-containing divalent group; X denotes a single bond or a divalent chain group; and R.sub.1 and R.sub.2 respectively denote a branch or linear chain group, R.sub.1 and R.sub.2 being the same or different.
    Type: Grant
    Filed: October 2, 1989
    Date of Patent: November 17, 1992
    Assignee: Canon Kabushiki Kaisha
    Inventors: Akira Tsuboyama, Yutaka Inaba, Akio Yoshida, Yukio Hanyu, Toshiharu Uchimi, Masataka Yamashita
  • Patent number: 5164968
    Abstract: A nine bit Gray code counter is constructed as a single integrated circuit such as a PLA and comprises D flip-flops, AND gates and Exclusive-OR gates. The array is programmed to provide a nine bit Gray code count at its outputs. The Q output of each flip-flop provides one bit in the Gray code count. The D input to each flip-flop is determined by the significance of the bit and the following equations: D0=A XOR Q0; D1=(A.multidot.Q0) XOR Q1; Dn=(A.multidot. . . . .multidot.Qn-2.multidot.Qn--1) XOR Qn; and Dmsb=(A.multidot.Q0.multidot.Q1.multidot. . . . .multidot.Qmsb-2 XOR Qmsb.
    Type: Grant
    Filed: October 15, 1991
    Date of Patent: November 17, 1992
    Assignee: Loral Aerospace Corp.
    Inventor: Kurt J. Otto
  • Patent number: 5164967
    Abstract: A pedometer for exercise such as walking and jogging, comprising the fact that an appropriate intensity of exercise is set by setting reference signals, which the user of the pedometer is permitted to hear with a sound producer or an earphone, thereby making it possible to render the user conscious of the exercise at the appropriate intensity and to count or measure and then display the number of steps of the exercise, the period of time thereof, and the continuation period of time thereof as associated with the set reference signals.
    Type: Grant
    Filed: September 4, 1990
    Date of Patent: November 17, 1992
    Assignee: Marutakairyoki Kabushiki Kaisha
    Inventors: Mikiya Endo, Mitsuhiro Ikeda
  • Patent number: 5162932
    Abstract: In a method of driving a liquid crystal matrix panel, the number of shifts of a voltage applied to each signal electrode from an ON level to an OFF level and vice versa is minimized in variation so that variation in the polarity inversion (or frequency) of a (driving) voltage applied to a corresponding pixel can be controlled. Accordingly, the disturbing effect of electrode resistance and liquid crystal capacitance can be reduced and thus, the uniformity of display will be ensured.
    Type: Grant
    Filed: October 18, 1990
    Date of Patent: November 10, 1992
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshinori Kobayashi, Yoshihiro Gohara, Shozo Fujiwara
  • Patent number: 5162678
    Abstract: A temperature compensation control circuit to maintain a constant control gain in an AGC (automatic gain control) amplifier. The present invention compensates for the inherent temperature dependence without using any special processing or non-standard device structures. The present invention utilizes the voltage drop across n diodes in series to produce the control voltage difference (V.sub.C -V.sub.C *). These n series diodes are coupled to the collectors of a PNP emitter coupled pair with emitter resistance. This causes the control voltage difference to be dependent on temperature (nkT/q), but this dependency cancels out with the other inherent temperature dependency in the exponential function of the AGC amplifier which is also produced by a diode form. Thus, the present invention provides temperature compensation with minimum component matching problems and without the need for a PTAT (proportional to absolute temperature) current source.
    Type: Grant
    Filed: September 18, 1990
    Date of Patent: November 10, 1992
    Assignee: Silicon Systems, Inc.
    Inventor: Richard G. Yamasaki
  • Patent number: 5160854
    Abstract: A level shifter, particularly suited for driving power stages for supplying power to integrated circuits, includes a DMOS transistor (40) which is driven by a digital signal source (42) and has a load resistor (44) as its drain load. A shifted output signal develops at the ends of said load resistor. The drain (V1) of the DMOS transistor is connected to the input of an inverter (46), while a Zener diode (54) and a second transistor (52) are connected in parallel with the load resistor (44), the gate of the second transistor (52) being driven by the output of the inverter (46). The output of the inverter (46) can be connected to the input of a drive stage (48), the output of which drives a power stage (50) for supplying power to an integrated circuit.
    Type: Grant
    Filed: July 24, 1991
    Date of Patent: November 3, 1992
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventors: Fabrizio Martignoni, Claudio Diazzi, Albino Pidutti, Fabio Vio
  • Patent number: 5160863
    Abstract: A programmable delay line with digital input to a two-part digital-to-analog converter structure to define an equivalent resistance at a pull-down node. Preferred embodiments are configured as two identical halves. The outputs of the two halves are combined to produce an exactly symmetrical waveform. This is particularly advantageous in a programmable delay line, since this architecture assures that control changes which change the delay will not also introduce asymmetry into the output waveform.
    Type: Grant
    Filed: June 30, 1989
    Date of Patent: November 3, 1992
    Assignee: Dallas Semiconductor Corporation
    Inventor: Titkwan Hui
  • Patent number: 5161041
    Abstract: An improved lighting assembly for a backlit electronic display includes an integrally formed image splitting/collimating lens for effectively enlarging the area illuminated by any one or part of one of the lamps of the source of backlighting. Through the use of the improved optical assembly described herein, there is provided a backlit electronic display characterized by fewer lamps, reduced heating, and vastly improved intensity of illumination per unit area in a lower profile package.
    Type: Grant
    Filed: April 26, 1990
    Date of Patent: November 3, 1992
    Assignee: OIS Optical Imaging Systems, Inc.
    Inventors: Adiel Abileah, Charles Sherman, Robert M. Cammarata
  • Patent number: 5160862
    Abstract: In order to rapidly reduce the magnetic energy of an inductive load (2), the driving voltage must be high. When the load (2) is disconnected via a MOSFET (3), then a premature activation of the MOSFET (3) given reversal of the voltage at the inductive load (2) must be prevented. A series circuit of a Zener diode and of a controllable switch (3) is connected between the gate and the load (2). A current source (depletion MOSFET 5) whose current is lower than the current that would flow upon Zener breakdown is connected between the gate and the source of the power MOSFET (1). The MOSFET (3) becomes conductive upon Zener breakdown and the energy is quickly reduced by a high voltage, essentially by the Zener voltage.
    Type: Grant
    Filed: November 6, 1991
    Date of Patent: November 3, 1992
    Assignee: Siemens Aktiengesellschaft
    Inventors: Ludwig Leipold, Hubert Rothleitner, Rainald Sander, Jenoe Tihanyi
  • Patent number: 5159217
    Abstract: A brownout reset generator includes a presettable counter and a reset controller consisting of a plurality of logic gates coupled to receive a brownout signal representing a power brownout condition or power assertion (i.e. power-up) and a clock signal, and to generate a brownout reset in response to and of selectively longer duration than the brownout signal. Following the leading edge of the brownout signal (i.e. initiation of the brownout condition), the counter is preset to a selected value and remains preset for the duration of the brownout signal. Following the trailing edge of the brownout signal (i.e. termination of the brownout condition), the counter begins counting clock pulses. The counter outputs a timing pulse after a selected number of clock pulses representing a predetermined time interval have been counted.
    Type: Grant
    Filed: July 29, 1991
    Date of Patent: October 27, 1992
    Assignee: National Semiconductor Corporation
    Inventors: Gordon L. Mortensen, Neal L. Horovitz
  • Patent number: 5159213
    Abstract: A logic gate circuit of TTL, ECL or other configuration, having an output stage including at least one transistor and a control transistor which switches the output stage to either a low or high conductive state in accordance with an input logic control signal supplied to the control transistor. In order to limit the transient change in potential of the internal voltage supply lines of the logic circuit relative to the external voltage supply to which they are connected, which occurs during logic state transitions, the base-emitter path of the output transistor is shunted by the collector-emitter path of a current bypass transistor the base of which is driven by the control transistor. The output transistor may be a composite equivalent transistor formed by a Darlington-connected pair of transistors, and the bypass transistor may itself be such a composite transistor.
    Type: Grant
    Filed: June 7, 1990
    Date of Patent: October 27, 1992
    Assignee: North American Philips Corporation
    Inventor: Derrell Q. Johnson
  • Patent number: 5159279
    Abstract: A circuit is provided for detecting out-of-lock condition in a phase lock loop. The phase lock loop receives a first signal having a first frequency and a voltage controlled oscillator of the phase lock loop produces a second signal having a second frequency. The circuit comprises a first data flip-flop coupled to the phase lock loop for receiving the first signal and clocked by the second signal. The first flip-flop produces an inverted output of the first signal. A second flip-flop is coupled to the phase lock loop for receiving the second signal clocked by the first signal, and produces a non-inverted output of the second signal. Additionally, an EXCLUSIVE-OR gate is coupled to the first and second flip-flops for receiving the inverted and non-inverted output thereof and producing a signal indicative of an out-of-lock condition.
    Type: Grant
    Filed: November 27, 1990
    Date of Patent: October 27, 1992
    Assignee: DSC Communications Corporation
    Inventors: Kishan Shenoi, David J. Wetle
  • Patent number: 5159206
    Abstract: A circuit to generate a power up reset pulse for a semiconductor device, such as a dynamic random access memory (DRAM) that may utilize an on chip voltage generator is disclosed. The circuit generates a positive going pulse when the external power supply ramps up. The pulse disappears when the voltage level within the device reaches a predetermined value of the external supply voltage. The circuit includes a CMOS inverter that is biased between the external voltage and ground and has its input coupled to the internally regulated voltage. The gate of a pull down transistor may couple the input of the CMOS inverter to the internally regulated voltage. A pull up transistor that is biased by the external voltage and whose gate is connected to the output of the CMOS inverter, is connected to the input of the CMOS inverter. Other elements may be added to enhance the circuits performance.
    Type: Grant
    Filed: July 31, 1990
    Date of Patent: October 27, 1992
    Inventors: Ching-Yuh Tsay, Donald J. Redwine
  • Patent number: 5157283
    Abstract: Disclosed is a decoder circuit designed to reduce the number of transistor elements and to increase the speed of operation. The decoder includes a plurality of output selectors for respectively drawing out different decoded output signal lines in group having the common input components. In each output selector, a plurality of serial-connected transistors is provided to execute AND operations for the common input components, and a plurality of parallel-connected transistors to execute OR operation for the remaining and their remaining inverted input components. The final one of the serial-connected transistors is coupled to each of parallel-connected transistors, and thereby the entire AND operation results for the common inputs and remaining inputs, or for the common inputs and remaining inverted inputs is obtained at the predetermined one of the decoded output signal lines.
    Type: Grant
    Filed: October 2, 1991
    Date of Patent: October 20, 1992
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Tae-hun Kin
  • Patent number: 5157523
    Abstract: A projection type liquid crystal display unit has dichroic mirrors capable of dividing a light from a light source into R, G and B components which are guided along respective light paths. Each of at least two of these light paths in provided with an optical system which includes a pair of polarizing plates, a twist nematic liquid crystal and at least one phase plate. The angles of the retardation phase axis of the phase plate and light-interruption axes of the polarizing plates or, alternatively, the retardation of the phase plate is determined so as to improve the light-interruption of the liquid crystal panel in light-interruption mode, thereby enhancing contrast of the display image.
    Type: Grant
    Filed: March 23, 1990
    Date of Patent: October 20, 1992
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Nobuyasu Yamagishi, Hiroshi Watanabe, Kazuo Yokoyama
  • Patent number: 5157525
    Abstract: The contrast or absolute brightness of a multiplexed LCD is maintained at its preselected value using a feedback arrangement which includes an LCD element functioning as a reference element. The reference element is not used to display information but is continually driven ON and OFF. The average transmissivity of the ON and OFF states is determined and compared with a reference value, the result of the comparison being used to control the voltage levels of the drive waveforms applied to the LCD. By selecting appropriate ratios between the ON and OFF times of the reference element, the LCD can be operated to give optimum contrast, or may have its absolute brightness varied. Control may be effected remotely by reprogramming the microprocessor which determines the timing of the drive waveforms.
    Type: Grant
    Filed: October 23, 1990
    Date of Patent: October 20, 1992
    Assignee: EEV Limited
    Inventors: Timothy J. Eaton, Roger J. Pittock
  • Patent number: 5157527
    Abstract: Top coat (4, 6) for a color filter (3) which is hard enough to resist the pressure of spacers (13) and whose edges (6) are slanted in such a way that a satisfactory step coverage is possible, formed by means of a flexographic pressing method, is a cured acrylic resin.
    Type: Grant
    Filed: February 12, 1991
    Date of Patent: October 20, 1992
    Assignee: U.S. Philips Corporation
    Inventors: Gerardus C. M. De Keyzer, Antonius H. M. Raaijmakers, Petrus E. M. Baltussen, Henricus G. J. A. M. Luijben
  • Patent number: 5157278
    Abstract: The present invention relates to a substrate voltage generator for a semiconductor device, comprising an oscillator for generating an oscillating signal to compensate the resistance value with temperature, a voltage pump driver for providing clock signals, a voltage pump for generating substate voltage, a level detector for detecting the substrate voltage, and a oscillating driver for providing the bias voltage, wherein the power consumption in the standby state of semiconductor devices can be reduced and the driving capacity is not variable even though the temperature is changed.
    Type: Grant
    Filed: October 30, 1990
    Date of Patent: October 20, 1992
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong Sun Min, Dong Il Seo