Abstract: A range selecting impedance is switched into or out of a parallel range-selecting network by connecting the impedance across the network through an n-channel and a p-channel FET connected in parallel output configuration. The n-channel FET does the switching if the drains are negative with respect to the sources. The p-channel FET does the switching if the drains are positive with respect to the sources. Each FET is controlled by a gate drive whose output waveform is varied to select the rate at which the FETs switch. In cases of several different switched range impedances, the FETs are used to switch the smallest impedance into the network, another range impedance is selected, and then the FETs used to switch the smallest impedance out of the network. In this way, fast glitch-free range switching is achieved.

Abstract: An output of a power-on-reset (POR) circuit is coupled to another circuit which needs to have the logic states thereof reset during each time a power supply used to power same is switched on. The POR circuit includes a first input circuit for generating an output signal that tracks the power supply output voltage Vdd approximately a first predetermined threshold below Vdd, as Vdd ramps up and further includes a second input circuit which generates an output signal which tracks approximately a second predetermined threshold above a second fixed voltage level, e.g., ground. The POR circuit further includes a comparator which compares the output signals from the first and second input circuits and switches an output signal thereof from a first to a second logic state once the input circuit output signals cross each other. A buffer is typically coupled to the output of the comparator to limit loading on same so as not to affect the comparator switching point.

Abstract: In a semiconductor phase synchronizing circuit, variations in specific frequency and damping factor due to unavoidable variations in manufacturing conditions are prevented so that variations in phase synchronizing characteristics from one product to another are reduced. A charge pump of the phase synchronizing circuit is provided with a proportional charging electric current source and a proportional discharging electric current source arranged to be in the form of a feedback loop and to pass to a loop filter charging/discharging electric currents which are proportional to a converted electric current (output electric current) of a V/I converting circuit. The proportional charging electric current source is a P-type MOSFET, while the proportional discharging electric current source is an N-type MOSFET. The charge pump is a current mirror circuit in front of which a current mirror circuit of the V/I converting circuit is disposed.

Abstract: A latch circuit including at least three gate circuits, and a noise resistance circuit. A first gate circuit (3, 4, 11, 16) receives a data signal (DT) and a clock signal (CLK). A second gate circuit (1, 7, 13, 17) is connected to an output of the first gate circuit. A third gate circuit (2, 5, 12 18) receives a first inverted clock signal (CLK) at an input terminal. A second input terminal of the third gate circuit is connected to an output of the second gate circuit and is a first output terminal is connected to an input terminal of the second gate circuit, so that a feedback line is formed between the second and third gate circuits. The noise resistance circuit (8, 9, 20, 21) has at least a signal delay element in the feedback line. The noise resistance circuit may include a filter circuit. The noise resistance circuit may also include an amplifier circuit.

Abstract: A multiple synchronized agile pulse generator is configured as high speed digital/analog test apparatus for providing complex patterns associated with modern avionics systems. The multiple synchronized agile pulse generator includes a network of counters and random access memory (RAM) banks which allow for predetermined hopping of pulse repetition intervals, pulse widths, pulse patterns, pulse amplitudes, and combinations of the above.

Abstract: A current switching circuit includes first and second FETs of the same channel type whose drain-source paths are commonly connected at one end and whose gates are connected to receive logic input signals in an inverted relation, and the other end of the drain-source path of the first FET is connected to an external circuit. The current switching circuit further includes a bipolar transistor connected to a commonly connected node between the drain-source paths of the first and second FETs.

Abstract: A liquid crystal display unit uses a photoconductive type liquid crystal light valve. By using non-monochromatic light as the writing light, the light excitation can be induced near the surface layer of the photoconductive layer by light of a shorter wavelength and also on portions deep in the layer by light of a longer wavelength. Thus, it is possible to induce the light excitation effectively on the photoconductive layer even when it is thick.

Abstract: A clock alignment circuit is responsive to a high speed clock signal for generating a low speed clock signal. A clock generator circuit monitors the phase difference between the high speed clock signal and the low speed clock signal and develops a control signal in response thereto during a time slot window signal for adjusting the transitions of the low speed clock signal to align with the high speed clock signal. The clock generator circuit is placed in the vicinity of the associated utilization circuit to that the low speed and high speed clock signals maintain alignment.

Abstract: A frequency synthesizer comprising at least two main PLL's, where each PLL has programmable dividers in both its input path (M and P) and its feedback path (N and Q), and where the first PLL is driven by a reference source of frequency F.sub.ref and has output Fl=(.sup.N /.sub.M) *F.sub.ref, and where this output serves as the input to the second main PLL, whose output in turn is F.sub.out =(.sup.Q /.sub.P) *Fl=(.sup.Q /.sub.P)*(.sup.N /.sub.M)*F.sub.ref, and each of the programmable counters is controlled by a calculation and control means, said synthesizer utilizing a method to produce an output frequency F.sub.out that is a close approximation to a requested frequency F.sub.req. The method includes doing several approximations to the ratio .sup.F req/F.sub.ref, and picking the best, calculating the four integers, generating several signals, and dividing them by said integers, locking said loops, and thereby producing F.sub.out. In one form of the invention, an approximation .sup.X 1/Y.sub.

Abstract: A programmable delay circuit of the present invention is comprised of an input terminal to which an input signal to be delayed is supplied, N (N.gtoreq.

Abstract: A timing delay circuit includes a first transistor having a control electrode coupled to an input terminal, a reference electrode coupled to a first DC bias terminal and an output electrode coupled to an output terminal of the timing delay circuit. The timing delay circuit further includes a second transistor having a control electrode coupled to the input terminal, a reference electrode coupled to a second DC bias terminal and an output electrode. The timing delay circuit further includes a third transistor having a control electrode coupled to the output electrode of the second transistor, a reference electrode coupled to the second DC bias terminal and an output electrode coupled to the output terminal of the timing delay circuit.

Abstract: A programmable delay line with digital input to a two-part digital-to-analog converter structure to define an equivalent resistance at a pull-down node. Preferred embodiments are configured as two identical halves. The outputs of the two halves are combined to produce an exactly symmetrical waveform. This is particularly advantageous in a programmable delay line, since this architecture assures that control changes which change the delay will not also introduce asymmetry into the output waveform.

Abstract: An improved liquid crystal device is described. The distance between a pair of substrates is kept constant by means of spacers interposed therebetween. The spacers consist of two kinds of spacers. One kind of spacers is fusable and functions to prevent the distance from expanding. The other kind of spacers is non-fusable and functions to prevent the distance from contracting.

Abstract: A liquid crystal color display provides a transmitted light output that is of one or more colors, black and/or white, as a function of the color of the incident light input and controlled energization or not of respective optically serially positioned liquid crystal color layers and/or multicolor composite liquid crystal color layer(s) in the display. Each liquid crystal layer may include plural volumes of operationally nematic liquid crystal material in a containment medium that tends to distort the natural liquid crystal structure in the absence of a prescribed input. Each layer includes a dye mixed with the liquid crystal material so as to have a particular coloring effect on light incident thereon. By selectively energizing or not respective portions of respective liquid crystal color layers, a multi-color light output can be produced. Such light output may be employed in a liquid crystal display that produces stationary or moving images.

Abstract: An optical head device has a light source for emitting a light, a polarizing element for converting the linearly polarized emitted light into a concentric-circle polarized light or a radially polarized light, a concentric grating coupler through which the polarized light is introduced into a waveguide layer, and another polarizing element for converting the light radiated from the waveguide layer into a linearly polarized light. The light is applied to and reflected by the surface of an optical disk and introduced into the waveguide layer again as a concentric-circle polarized light or radially polarized light due to reversability of light, whereby the reflected light is detected. Each of the polarizing elements has a twist nematic liquid crystal layer having a linearly oriented liquid crystal orientation surface and a concentric-circle oriented liquid crystal orientation surface.

Abstract: An electrical contact for use with an optically responsive, polymer dispersed liquid crystal film is provided. The preferred electrical contact means consists of a pair of U-shaped, electrically conductive spring connectors. Each of these spring connectors is rigidly biased against corresponding transparent electrodes provided on each of the surrounding transparent substrates, so as to provide a compressive clamping force against the electrode. This ensures an intimate and complete electrical connection between each spring connector and each transparent electrode. The spring connector may be formed from any electrically conductive material which is sufficiently strong yet yielding and which is sufficiently anodic with respect to the electrode material, a preferred material being a suitable beryllium copper alloy when the electrodes are formed from a material such as indium-tin oxide.

Abstract: A signal transmission circuit which transmits a signal over a transmission line includes a line driver circuit comprising a differential amplifier and an emitter follower circuit connected thereto, and a metal oxide semiconductor field-effect transistor which provides a high impedance when power supply from a power supply source is turned off and, thereby, causes the line driver circuit to provide a high output impedance to the transmission line when power supply is turned off.

Abstract: A switched-capacitor circuit is described, which performs the functions of a full-wave rectifier and of an integrator and has a single operational amplifier and a comparator. The circuit is insensitive to the stray capacitances and offsets of the comparator and the operational amplifier. In particular, the input signal is sampled during only one phase of the clock which pilots the operation of the switched-capacitance network.

Abstract: The projection-type display device has a light source emitting a parallel luminous flux, a liquid crystal light valve disposed on the luminous flux and outputs a rectangular two-dimensional image to be projected on a screen, and a projection lens magnifying the rectangular two-dimensional image output. The light source has a first concave mirror (parabolic mirror) the reflective surface of which is oriented in the direction of emission of the luminous flux, a lamp laced in front of the first concave mirror, and a second concave mirror (parabolic mirror or spherical mirror), the reflective surface of which is oriented toward the first concave mirror. In the second concave mirror is formed an aperture window, which is a rectangle of substantially similar to that of the liquid crystal light valve and emits a rectangular luminous flux.

Abstract: Synchronization pulses for an internal combustion engine are generated by identifying the second of two consecutive pulses of the same polarity in a pulse train of positive going and negative going pulses. An evaluation pulse sequence is generated which switches from a low level to a high level in response to a positive going pulse and from the high level to a low level in response to a negative going pulse. A synchronization pulse is generated in response to a differentiated pulse derived from the pulse train when the level of the evaluation pulse sequence indicates that a switching pulse of said same polarity as that of the differentiated pulse has just occurred.