Abstract: A data latching circuit includes a standard clock qualified transparent latch cell which receives an input data signal and an enable signal. The input data signal is also asserted at the input of a first transistor gate circuit which is controlled by the enable signal. The output of the transparent latch is asserted at the input of a second transistor gate circuit which is controlled by an inverted enable signal. The outputs of the two transistor gate circuits, only one of which is active at any time, are combined and buffered for output.

Abstract: A liquid crystal display includes a plurality of laminated liquid crystal layers and a transparent substrate interposed between the liquid crystal layers, the transparent substrate being formed of an aggregate of optical fibers arranged so that a ray may be introduced between main and back surfaces of the substrate, whereby aberration of a display image of adjacent liquid crystal layers caused by a difference of a viewing angle can be prevented.

Abstract: A CMOS bus driver circuit with improved speed attributable to reduced capacitive loading on a control signal line and reduced capacitance added to the capacitance of a bus line. In one form, the bus driver circuit comprises a P-channel transistor and two N-channel transistors. The P-channel transistor has its current conducting path connected between a data line signal and a control electrode of the first N-channel transistor, and receives a control signal on its control electrode. A first N-channel transistor has its current conducting path connected between the bus line and a power supply voltage terminal. A second N-channel transistor has its current path connected between the gate of the first N-channel transistor and the power supply voltage terminal, and receives the control signal on its control electrode.

Abstract: A spatial light modulator providing an improved contrast, has a laminated structure of multiple layers including typically a photoconductive layer, an optical modulation layer, and a pair of electrode layers interposing the photoconductive and optical modulation layers. The thickness of at least one of the electrode layers having a predetermined relationship with a wavelength of light incident to the one of the electrode layers for writing or reading-out information into or from the spatial light modulator.

Abstract: A double-layered type super-twisted liquid crystal display device including a display cell and a compensating cell in a laminated structure with a spacer interposed therebetween wherein the compensating cell is arranged on the front surface side of the display device. The display cell is arranged on the rear surface side of the display device, and a light source for illuminating the display cell as well as a reflector are arranged on the rear surface side of the display cell. In addition, a transparent electrode is formed over the whole surface of at least one of glass substrates constituting the compensating cell. The transparent electrode is earthed via a clip pin which is held in a clamped state at the outermost end part of the transparent electrode.

Abstract: A liquid crystal display device comprises first and second substrates disposed to face each other, first and second electrodes formed on the both substrates to opposed to each other and forming a display region, signal leads formed on the second substrate and connected to the second electrodes, a seal surrounding the display region between the substrates and connecting together the substrates, a driving circuit provided between outer edges of the display region and those of the seal and connected to the leads, for generating a driving signal and supplying the signal to the wires in response to externally input display data, and a liquid crystal material sealed in a space surrounded by the substrates and seal.

Abstract: A holding circuit used in a pedestal level clamp circuit of a color television receiver. By using base current of a transistor as charging current of a capacitor, a large time constant is obtained. Also, in case the voltage lower than the reference voltage is held, base current of the transistor is used as discharging current to discharge slowly. Furthermore, though a charging transistor of the capacitor must be a PNP type and a discharging transistor must be an NPN type, it is designed not to be influenced by the difference in current amplification factors of the two types.

Abstract: An adaptable MOS winner take all circuit includes a plurality of adaptable current mirrors. Each adaptable current mirror includes a floating node onto which and from which electrons may be transported by control signals and electrical semiconductor structures. Electrons may be placed onto and removed from a floating node associated with at least one MOS insulated gate field effect transistor, usually the gate of the transistor, in an analog manner, by application of first and second electrical control signals. A first electrical control signal controls the injection of electrons onto the floating node from an electron injection structure and the second electrical control signal controls the removal of electrons from the floating node by an electron removal structure.

Abstract: In a switching circuit formed as an integrated circuit, a series circuit comprising a diode (D.sub.1) and a resistor (R.sub.1) is connected between a base and an emitter of an npn transistor (TR.sub.1) requiring a high speed switching operation. Therefore, a high speed operation is made possible. Furthermore, in a circuit constructed such that the above npn transistor is driven by a pnp transistor (TR.sub.3, TR.sub.4), a leakage current produced in the above pnp transistor at high temperature is allowed to flow in the above series circuit. Accordingly, a malfunction of the above npn transistor is prevented. Consequently, an integrated circuit operable even under high temperatures is achieved.

Abstract: An apparatus is provided for delaying digital data signals by fixed amounts within an integrated circuit. A delay lock loop includes an adaptive delay line, a phase detector and an integrator. The integrator provides control signals c.sub.p, c.sub.n for controlling the delay line, in dependence upon the relative phase of a reference clock signal .phi..sub.0 and a delayed clock signal .phi..sub.n. The delay line includes a plurality of delay cells. By maintaining a phase relationship .phi..sub.n =.phi..sub.0 +360.degree. one clock cycle, T.sub.c, delay through the delay line is provided. Thus each delay cell provides T.sub.c /n delay. By placing identical cells in signal paths elsewhere on a chip, fixed delays can be introduced which are controlled by the delay lock loop.

Abstract: A backlighted liquid crystal display (LCD) system with a light source and a light pipe which is separated from the LCD panel by an air gap to facilitate uniform brightness of the viewing area. The air gap effectively blocks conductive heat transfer from the light source to the LCD panel. The LCD panel is enframed within a metal frame that serves as a heat sink which prevents a temperature gradient across the LDC panel. The light source is fastened to the light pipe and remaining exposed areas of the light source are covered with an insulating material to trap heat and prevent heat radiation to the LCD panel. A sheet of heat conductive material, which lines the inner back surface of a plastic enclosure surrounding the LCD display assembly, serves to equally distribute heat throughout the inner area of the enclosure. The exposed surface of the heat conductive lining is preferably blackened.

Abstract: An updown counter up-counts binary data stored in respective flip-flops in an up-count mode, and down-counts the binary data stored in the respective flip-flops in a down-count mode. When a command for an up-count mode is applied by an up/down control signal, the binary data stored in the respective flip-flops is converted into a complement on two after converting it into a complement on one. When a command for a down-count mode is applied by an up/down control signal, the binary data stored in the respective flip-flops is converted into a complement on one after converting it into a complement on two. The converted data is used to rewrite the data stored in the respective flip-flops.

Abstract: An active matrix liquid crystal display device has diamond-shaped pixels arrayed in a close-packed arrangement, and interconnected by row and column electrodes which zigzag between the pixels, each column electrode extending between and being common to two columns of pixels and their associated thin film switches, and the column electrode-switch connections alternating sequentially between pixel columns.

Abstract: A circuit for providing a glitch-proof, powered-down inactive state to a memory array is disclosed. Cross-coupled NAND gates provide non-overlapping true/complement outputs for an on-chip receiver. Stable inactivation of both true and complement outputs is ensured without performance degrading delay stages.

Abstract: A semiconductor memory device having a substrate voltage production circuit comprises a time delay circuit. The time delay circuit of the present invention has a simple construction and is provided to facilitate removal of an unwanted substrate current I.sub.SUB existing during a precharge cycle of memory operation. The substrate voltage production circuit requires no additional regulating signals for operation. Latch-up conditions commonly caused by such unwanted substrate currents are eliminated and stable semiconductor memory device operation is achieved.

Abstract: A driving circuit for driving a floating circuit (28) responsive to a digital signal (IN) includes two DMOS transistors (10, 12) which are driven in opposite phase on their respective gates starting from the digital signal. The two DMOS transistors are biased by a current source which is formed by a current mirror (16, 18), which mirrors a reference current (I.sub.BIAS), and by an auxiliary circuit (34-44) for injecting an additional current pulse during switching. Two MOS transistors (20, 22) serve as the respective loads for the two DMOS transistors. The MOS transistors can be P-channel transistors, in which event the gate of each MOS transistor (20, 22) can be connected to the drain of the other MOS transistor. Two Zener diodes (24, 26) can be employed to limit the voltage between the gate and source of the respective MOS transistor. The driving output of the floating circuit (28) can be the drain of one of the DMOS transistors.

Abstract: A semiconductor integrated circuit device having an analogue signal processing circuit and a digital signal processing circuit formed on a single semiconductor substrate is disclosed. As an example of the analogue signal processing circuit, a voltage comparator is described. Being liable to be affected by noise, an inverter 2 is formed of an NMOS transistor 41 and a resistance R. For transistor 41 is formed in a well region having a conductivity type (p) opposite to the conductivity type of the substrate (n), it is not easily influenced by noise transmitted through the substrate. Therefore, a voltage comparator independent of the adverse effect of noise from the digital signal processing circuit is obtained.

Abstract: A range selecting impedance is switched into or out of a parallel range-selecting network by connecting the impedance across the network through an n-channel and a p-channel FET connected in parallel output configuration. The n-channel FET does the switching if the drains are negative with respect to the sources. The p-channel FET does the switching if the drains are positive with respect to the sources. Each FET is controlled by a gate drive whose output waveform is varied to select the rate at which the FETs switch. In cases of several different switched range impedances, the FETs are used to switch the smallest impedance into the network, another range impedance is selected, and then the FETs used to switch the smallest impedance out of the network. In this way, fast glitch-free range switching is achieved.

Abstract: In a liquid crystal projection color display apparatus having three liquid crystal display devices used for red, green and blue light, each liquid crystal display device has a liquid crystal display panel and a microlens array disposed on the light-source side or the light-source and screen sides of the liquid crystal display panel. The microlens array has a controllable refractive power which is controlled by applying an electrtical power thereto. An electrical voltage is applied between transparent electrodes formed on both surfaces of a microlens array so that the refractive power of the microlens array can be made a value adapted to suit the corresponding one of red, green and blue light.

Abstract: A programmable delay line with digital input to a two-part digital-to-analog converter structure to define an equivalent resistance at a pull-down node. Preferred embodiments are configured as two identical halves. The outputs of the two halves are combined to produce an exactly symmetrical waveform. This is particularly advantageous in a programmable delay line, since this architecture assures that control changes which change the delay will not also introduce asymmetry into the output waveform.