Abstract: A driving circuit suitable for driving a capacitive load such as an EL display panel is disclosed, which comprises a first power source terminal; a second power source terminal; an output terminal, with which a capacitive load is connected; a source side thyristor connected between the first power source terminal and the output terminal, and supplying current to the load; a sink side thyristor connected between the second power source terminal and the output terminal and drawing-out current from the load; and a control section connected between the first power source terminal and the second power source terminal and ON-OFF controlling the source side thyristor and the sink side thyristor through a circuit arrangement coupled between the control circuit and the gates of the thyristors.

Abstract: Capacitance compensation techniques are used to reduce capacitive effects that impact on the performance of current steering circuits (FIG. 1). In an isolation technique (FIGS. 2a-2e), a resistor (R) or a diode (D) is coupled to a data-switched transistor to dampen voltage perturbations associated with the gate-to-source capacitance. In a design variable technique FIGS. 3a-3d), a transistor (PDV) is included in either the output or ground legs of the current steering circuit to provide a design variable to counteract the capacitive effects of the associated data-switched (PDX/NDX) or voltage-controlled (PREF) transistor. In a bipolar substitution technique (FIG. 4), a data-switched bipolar transistor (QDX) is substituted for the data-switched MOS transistor, and made sufficiently small to significantly reduce junction capacitance. In addition, capacitive effects can be reduced by introducing fabrication alterations (FIGS.

Abstract: Two p-channel MOS transistors are inserted in series between the positive power supply and the output terminal, whereas two n-channel MOS transistors are inserted in series between the output terminal and the negative power supply. Across the source and drain of one of the p-channel MOS transistors, a first diode is connected in parallel in the forward direction. Similarly, across the source and drain of one of the n-channel MOS transistors, a second diode is connected in parallel in the forward direction.

Abstract: A liquid crystal display includes a plurality of laminated liquid crystal layers and a transparent substrate interposed between the liquid crystal layers, the transparent substrate being formed of an aggregate of optical fibers arranged so that a ray may be introduced between main and back surfaces of the substrate, whereby aberration of a display image of adjacent liquid crystal layers caused by a difference of a viewing angle can be prevented.

Abstract: A CMOS bus driver circuit with improved speed attributable to reduced capacitive loading on a control signal line and reduced capacitance added to the capacitance of a bus line. In one form, the bus driver circuit comprises a P-channel transistor and two N-channel transistors. The P-channel transistor has its current conducting path connected between a data line signal and a control electrode of the first N-channel transistor, and receives a control signal on its control electrode. A first N-channel transistor has its current conducting path connected between the bus line and a power supply voltage terminal. A second N-channel transistor has its current path connected between the gate of the first N-channel transistor and the power supply voltage terminal, and receives the control signal on its control electrode.

Abstract: A liquid crystal display device comprises first and second substrates disposed to face each other, first and second electrodes formed on the both substrates to opposed to each other and forming a display region, signal leads formed on the second substrate and connected to the second electrodes, a seal surrounding the display region between the substrates and connecting together the substrates, a driving circuit provided between outer edges of the display region and those of the seal and connected to the leads, for generating a driving signal and supplying the signal to the wires in response to externally input display data, and a liquid crystal material sealed in a space surrounded by the substrates and seal.

Abstract: A spatial light modulator providing an improved contrast, has a laminated structure of multiple layers including typically a photoconductive layer, an optical modulation layer, and a pair of electrode layers interposing the photoconductive and optical modulation layers. The thickness of at least one of the electrode layers having a predetermined relationship with a wavelength of light incident to the one of the electrode layers for writing or reading-out information into or from the spatial light modulator.

Abstract: An active matrix liquid crystal display device has diamond-shaped pixels arrayed in a close-packed arrangement, and interconnected by row and column electrodes which zigzag between the pixels, each column electrode extending between and being common to two columns of pixels and their associated thin film switches, and the column electrode-switch connections alternating sequentially between pixel columns.

Abstract: A backlighted liquid crystal display (LCD) system with a light source and a light pipe which is separated from the LCD panel by an air gap to facilitate uniform brightness of the viewing area. The air gap effectively blocks conductive heat transfer from the light source to the LCD panel. The LCD panel is enframed within a metal frame that serves as a heat sink which prevents a temperature gradient across the LDC panel. The light source is fastened to the light pipe and remaining exposed areas of the light source are covered with an insulating material to trap heat and prevent heat radiation to the LCD panel. A sheet of heat conductive material, which lines the inner back surface of a plastic enclosure surrounding the LCD display assembly, serves to equally distribute heat throughout the inner area of the enclosure. The exposed surface of the heat conductive lining is preferably blackened.

Abstract: A circuit for providing a glitch-proof, powered-down inactive state to a memory array is disclosed. Cross-coupled NAND gates provide non-overlapping true/complement outputs for an on-chip receiver. Stable inactivation of both true and complement outputs is ensured without performance degrading delay stages.

Abstract: In a switching circuit formed as an integrated circuit, a series circuit comprising a diode (D.sub.1) and a resistor (R.sub.1) is connected between a base and an emitter of an npn transistor (TR.sub.1) requiring a high speed switching operation. Therefore, a high speed operation is made possible. Furthermore, in a circuit constructed such that the above npn transistor is driven by a pnp transistor (TR.sub.3, TR.sub.4), a leakage current produced in the above pnp transistor at high temperature is allowed to flow in the above series circuit. Accordingly, a malfunction of the above npn transistor is prevented. Consequently, an integrated circuit operable even under high temperatures is achieved.

Abstract: A driving circuit for driving a floating circuit (28) responsive to a digital signal (IN) includes two DMOS transistors (10, 12) which are driven in opposite phase on their respective gates starting from the digital signal. The two DMOS transistors are biased by a current source which is formed by a current mirror (16, 18), which mirrors a reference current (I.sub.BIAS), and by an auxiliary circuit (34-44) for injecting an additional current pulse during switching. Two MOS transistors (20, 22) serve as the respective loads for the two DMOS transistors. The MOS transistors can be P-channel transistors, in which event the gate of each MOS transistor (20, 22) can be connected to the drain of the other MOS transistor. Two Zener diodes (24, 26) can be employed to limit the voltage between the gate and source of the respective MOS transistor. The driving output of the floating circuit (28) can be the drain of one of the DMOS transistors.

Abstract: An updown counter up-counts binary data stored in respective flip-flops in an up-count mode, and down-counts the binary data stored in the respective flip-flops in a down-count mode. When a command for an up-count mode is applied by an up/down control signal, the binary data stored in the respective flip-flops is converted into a complement on two after converting it into a complement on one. When a command for a down-count mode is applied by an up/down control signal, the binary data stored in the respective flip-flops is converted into a complement on one after converting it into a complement on two. The converted data is used to rewrite the data stored in the respective flip-flops.

Abstract: A semiconductor memory device having a substrate voltage production circuit comprises a time delay circuit. The time delay circuit of the present invention has a simple construction and is provided to facilitate removal of an unwanted substrate current I.sub.SUB existing during a precharge cycle of memory operation. The substrate voltage production circuit requires no additional regulating signals for operation. Latch-up conditions commonly caused by such unwanted substrate currents are eliminated and stable semiconductor memory device operation is achieved.

Abstract: An adaptable MOS winner take all circuit includes a plurality of adaptable current mirrors. Each adaptable current mirror includes a floating node onto which and from which electrons may be transported by control signals and electrical semiconductor structures. Electrons may be placed onto and removed from a floating node associated with at least one MOS insulated gate field effect transistor, usually the gate of the transistor, in an analog manner, by application of first and second electrical control signals. A first electrical control signal controls the injection of electrons onto the floating node from an electron injection structure and the second electrical control signal controls the removal of electrons from the floating node by an electron removal structure.

Abstract: A semiconductor integrated circuit device having an analogue signal processing circuit and a digital signal processing circuit formed on a single semiconductor substrate is disclosed. As an example of the analogue signal processing circuit, a voltage comparator is described. Being liable to be affected by noise, an inverter 2 is formed of an NMOS transistor 41 and a resistance R. For transistor 41 is formed in a well region having a conductivity type (p) opposite to the conductivity type of the substrate (n), it is not easily influenced by noise transmitted through the substrate. Therefore, a voltage comparator independent of the adverse effect of noise from the digital signal processing circuit is obtained.

Abstract: An apparatus is provided for delaying digital data signals by fixed amounts within an integrated circuit. A delay lock loop includes an adaptive delay line, a phase detector and an integrator. The integrator provides control signals c.sub.p, c.sub.n for controlling the delay line, in dependence upon the relative phase of a reference clock signal .phi..sub.0 and a delayed clock signal .phi..sub.n. The delay line includes a plurality of delay cells. By maintaining a phase relationship .phi..sub.n =.phi..sub.0 +360.degree. one clock cycle, T.sub.c, delay through the delay line is provided. Thus each delay cell provides T.sub.c /n delay. By placing identical cells in signal paths elsewhere on a chip, fixed delays can be introduced which are controlled by the delay lock loop.

Abstract: A current switching circuit includes first and second FETs of the same channel type whose drain-source paths are commonly connected at one end and whose gates are connected to receive logic input signals in an inverted relation, and the other end of the drain-source path of the first FET is connected to an external circuit. The current switching circuit further includes a bipolar transistor connected to a commonly connected node between the drain-source paths of the first and second FETs.

Abstract: A liquid crystal display unit uses a photoconductive type liquid crystal light valve. By using non-monochromatic light as the writing light, the light excitation can be induced near the surface layer of the photoconductive layer by light of a shorter wavelength and also on portions deep in the layer by light of a longer wavelength. Thus, it is possible to induce the light excitation effectively on the photoconductive layer even when it is thick.

Abstract: A clock alignment circuit is responsive to a high speed clock signal for generating a low speed clock signal. A clock generator circuit monitors the phase difference between the high speed clock signal and the low speed clock signal and develops a control signal in response thereto during a time slot window signal for adjusting the transitions of the low speed clock signal to align with the high speed clock signal. The clock generator circuit is placed in the vicinity of the associated utilization circuit to that the low speed and high speed clock signals maintain alignment.