Abstract: In one embodiment, a method for preventing an operable state in a plurality of components of an information handling system in response to a reset of a power supply includes: receiving, by an embedded controller of the information handling system, power from the power supply after the reset of the power supply; causing a platform controller hub of the information handling system to receive the power from the power supply; receiving a signal from the platform controller hub indicating that the plurality of components should be placed in the operable state from an inoperable state; determining that the reset of the power supply was caused by the power supply being previously removed from the information handling system; determining that a position of a lid of the information handling system is in a closed position; and causing the plurality of components to remain in the inoperable state.

Abstract: An integrated circuit including an autosleep circuit and a voltage regulator. The autosleep circuit includes a latch, a voltage detection circuit outputting a signal to a set input of the latch responsive to a voltage at its input exceeding a threshold voltage, and a delay timer outputting a signal to a reset input of the latch responsive to inactivity at one or more input terminals. A voltage regulator is configured to generate a voltage for biasing a subsystem such as digital logic, and is also the input voltage to the voltage detection circuit. The voltage regulator includes a plurality of transistors in parallel, one gated by the output of the latch and each of the others gated by one of the one or more input terminals. The voltage regulator includes an output leg that generates the output voltage responsive to one of the parallel transistors being turned on.

Abstract: The present disclosure includes apparatuses and methods for providing energy information to memory. An embodiment includes determining, by a host, that a charge level of an energy source coupled to the host has reached or exceeded a threshold value, and transmitting, from the host to a memory device coupled to the host, signaling indicative of an energy mode for the memory device, wherein the signaling is transmitted based at least in part on determining that the charge level of the energy source has reached or exceeded the threshold.

Abstract: Disclosed is an apparatus for an application including a core device for the application. The apparatus includes a power (preferably RF energy) harvester connected to the core device to power the core device. Also disclosed is a method for an application. The method includes the steps of converting RF energy into usable energy. There is the step of powering the core device with the usable energy.

Abstract: Embodiments detailed herein include, but are not limited to, a hardware processor to execute instructions and security circuitry to perform pre-boot operations including signature verification of a portion of firmware in a firmware storage hardware and initiating recovery upon a signature verification failure. The hardware processor comprises a plurality of cores in some embodiments. The hardware processor a multicore processor in some embodiments.

Abstract: In an embodiment, a processor includes processing cores to execute instructions; and throttling logic. The throttling logic is to: determine an average capacitance score for execution events in a sliding window; perform frequency throttling when the average capacitance score exceeds a throttling threshold; determine a count of frequency throttling instances; and in response to a determination that the count of frequency throttling instances exceeds a maximum throttling value, increase the throttling threshold and concurrently reduce a baseline frequency. Other embodiments are described and claimed.

Abstract: A three-dimensional (3D) ultra-low power neuromorphic accelerator is described. The 3D ultra-low power neuromorphic accelerator includes a power manager as well as multiple tiers. The 3D ultra-low power neuromorphic accelerator also includes multiple cores defined on each tier and coupled to the power manager. Each core includes at least a processing element, a non-volatile memory, and a communications module.

Abstract: An access point, which is a Power over Ethernet (PoE) Powered Device (PD) measures input voltage and input current. The access point determines a power requirement of the access point based on the measured current, measured voltage, and information about power requirements of access point components or devices coupled to the access point a power requirement of the access point. The access point communicates the determined power request to a power sourcing equipment (PSE), e.g., a network switch. In some embodiments, the access point further communicates one of: measured input current and measured input voltage to the PSE. The PSE uses the information received from the access point, e.g., power request and power measurements to determine an amount of power to be granted to the access point. If the access point does not receive the requested power level the access point selects internal components and/or external devices to de-power.

Abstract: An apparatus includes memory arrays and a power-performance-endurance manager module. The power-performance-endurance manager module stores a power-endurance state descriptor data structure, which includes endurance levels associated with power-endurance modes. The manager module dynamically configures the apparatus to operate the memory arrays according to one of the power-endurance modes based on a desired endurance level.

Abstract: An apparatus is provided which comprises: a controller to allocate, to a component, a resource budget selected from a plurality of quantization levels; and a circuitry to adaptively update the plurality of quantization levels.

Abstract: Example implementations relate to system and method of managing transitioning of a computing system to a power-on state from a standby-power state. The computing system includes a manageability controller, an initialization controller, an auxiliary device, and a processor. In such examples, the manageability controller may first determine an initialization status of the auxiliary device from a data corresponding to the auxiliary device, when the computing system is transitioning from the standby-power state to the power-on state. In one or more examples, the initialization status may include the auxiliary device in an initialized stage or a non-initialized stage. Later, the manageability controller may direct the initialization controller to delay the transitioning of the computing system from the standby-power state to the power-on state, in response to determining that the initialization status of the auxiliary device is in the non-initialized stage.

Abstract: An integrated circuit includes a first processing domain configured to run a first operating system and a second processing domain configured to run a second operating system that is different than the first operating system. The integrated circuit further includes a time stamp timer circuit in the first processing domain configured to provide a first time stamp value to the first processing domain and an adjusted second time stamp value to the second processing domain. The time stamp timer circuit includes a timer adjust circuit configured to synchronize the adjusted second time stamp value when a power up signal is received by the time stamp timer circuit from the second processing domain.

Abstract: A processing method for reducing power consumption and a mobile terminal are provided. The method includes: controlling a sensor coprocessor to enter a dormant state, in a case that the mobile terminal is in a screen-off state; receiving a trigger instruction transmitted by a touch screen coprocessor, wherein the trigger instruction is transmitted when data collected by a sensor connected to the touch screen coprocessor meets a predetermined trigger condition; and controlling the mobile terminal to perform a function corresponding to the trigger s action.

Abstract: The technology described herein is related to a two-phase deployment-initiated wakeup mechanism for a body-mountable electronic device. During a first phase of the two-phase wakeup mechanism, a motion sensor detects an acceleration event indicative of deployment of the device onto the body of the user. During a second phase of the two-phase mechanism, control circuitry can be adapted to be enabled by the acceleration event. Once enabled, the control circuitry can verify that the device has been launched onto the body of a user via a deployment applicator in which the device is retained until deployment. Once verified, the control circuitry can wake up the body-mountable electronic device by transitioning the device from a sleep state to a functional (or operational) state.

Abstract: In accordance with one embodiment, a fan controller operates in a standard mode when main power is provided to the power supply unit in which speed of the fan is controlled in response to a primary pulse width modulation (PWM) signal from a power controller. A loss of the main power to the power supply unit may be detected at a logic circuit, which provides a secondary PWM signal to the fan controller in response to the loss of the main power. In certain embodiments, the fan controller is operated in a power loss mode in response to the secondary PWM signal to direct the speed of the fan to a low-power consumption target speed.

Abstract: For a neural network inference circuit that executes a neural network including multiple computation nodes at multiple layers for which data is stored in a plurality of memory banks, some embodiments provide a method for dynamically putting memory banks into a sleep mode of operation to conserve power. The method tracks the accesses to individual memory banks and, if a certain number of clock cycles elapse with no access to a particular memory bank, sends a signal to the memory bank indicating that it should operate in a sleep mode. Circuit components involved in dynamic memory sleep, in some embodiments, include a core RAM pipeline, a core RAM sleep controller, a set of core RAM bank select decoders, and a set of core RAM memory bank wrappers.

Abstract: In one embodiment, processor includes a first core to execute instructions, and a power controller to control power consumption of the processor. The power controller may include a hardware performance state controller to control a performance state of the first core autonomously to an operating system, and calculate a target operating frequency for the performance state based at least in part on an energy performance preference hint received from the operating system. Other embodiments are described and claimed.

Abstract: A system includes a processor coupled to an integrated circuit. The processor includes a non-volatile memory to store instructions to perform a boot process. The boot process is discontinued to prevent unauthorized use of the processor if a value received from the integrated circuit in response to a first value sent to the integrated is not valid.

Abstract: There is provided a recording apparatus. A recording control unit performs control to record a still image or a moving image into a first recording medium. A control unit controls whether to permit execution of automatic background processing during a power saving period on the first recording medium. The control unit performs control to permit the execution of the automatic background processing during the power saving period when the still image is recorded into the first recording medium, and not to permit the execution of the automatic background processing during the power saving period when the moving image is recorded into the first recording medium.

Abstract: Technology for a system operable to extend a level of processor performance is disclosed. The system can comprise a power source connected to a platform voltage regulator (VR) and one or more processors and configured to provide an input power to the platform VR. The system can further comprise the platform VR connected to a peripheral interface and the one or more processors and configured to power the peripheral interface and send a power good signal to the one or more processors. The system can further comprise the peripheral interface connected to the platform VR and the one or more processors and configured to connect to a peripheral device and send a signal to the one or more processors when a peripheral interface connection state is identified as connected.