Abstract: A method of polishing a semiconductor substrate surface having at least one ruthenium feature thereon and at least one dielectric material, wherein the substrate is contacted with an aqueous composition containing from about 0.0005 to about 1 moles/kilogram of periodic acid, from about 0.2% to about 6% % by weight of silica abrasive having an average particle size of about 50 nm or less, and an amine in an amount sufficient to adjust the pH of the composition to between about 2.5 and 7. The removal selectivity of the ruthenium to a. low-K dielectric is greater than 20:1. Advantageously, the substrate further has a tantalum-containing compound, and the polishing rate of the tantalum-containing compound is about the same as the polishing rate of the ruthenium, so that the polishing process is a one-step process.

Abstract: A plasma etching method for plasma-etching an anti-reflective coating formed on a target object includes the step of placing the target object into a processing chamber having a first electrode and a second electrode provided while facing each other, the target object including an etching target film, the anti-reflective coating and a patterned photoresist film sequentially formed in that order on a substrate. The plasma etching method further includes the steps of introducing a processing gas into the processing chamber; generating a plasma by applying a high frequency power to one of the first electrode and the second electrode; and applying a DC voltage to one of the first electrode and the second electrode.

Abstract: The present invention discloses a method of fabricating mirrors for LCOS (Liquid Crystal On Silicon) display device, including: forming a dielectric layer over a silicon substrate; forming a stop layer over the dielectric layer; forming an insulation layer over the stop layer; etching the insulation layer and the stop layer until the dielectric layer is exposed, thus forming an insulation fence; forming a metal layer over the dielectric layer and the insulation fence; and planarizing the metal layer and the insulation fence, hence the planarized insulation fence isolating the metal layer into mirror array. Therefore no pits can be generated in the metal layer and no pits can be generated in the mirrors formed subsequently, resulting in high quality mirror surface.

Abstract: A method for fabricating a microelectronic structure provides for forming a backfilling material layer at least laterally adjacent, and preferably laterally adjoining, a resist layer located over a substrate. Preferably, the resist layer comprises a surface treated resist layer. Optionally, the backfilling material layer may be surface treated similarly to the surface treated resist layer. Under such circumstances: (1) surface portions of the backfilling material layer and resist layer; and (2) remaining portions of the backfilling material layer and resist layer, may be sequentially stripped using a two step etch method, such as a two step plasma etch method. Alternatively, a surface portion of the surface treated resist layer only may be stripped while using a first etch method, and the remaining portions of the resist layer and backfilling material layer may be planarized prior to being simultaneously stripped while using a second etch method.

Abstract: After an external shape of a photoresist layer is patterned with use of a Cr film as an underlayer, i.e., a metal film to serve as an anticorrosive film that resists crystal etching, and an Au film as a surface layer, the Au film is etched. After groove portions are then patterned, the Cr film is etched. Since no degenerated-surface layer cannot be formed on the photoresist layer with an etchant for the Au film, the groove portions can be patterned without any degenerated-surface layer according to this method, so that high-accuracy groove portions can be formed.

Abstract: A method of manufacturing a liquid ejection head in which a pressure chamber for storing an ejection liquid is connected with an ink supply channel through a restrictor, includes the steps of: forming first spaces for the liquid supply channel and the pressure chamber in a silicon substrate by performing anisotropic etching on a surface of the silicon substrate, the surface of the silicon substrate being parallel to a Si(110) plane, each of the first spaces being defined by two vertical walls and two inclined walls, each of the two vertical walls being parallel to a Si(111) plane that is perpendicular to the surface of the silicon substrate, each of the two inclined walls being parallel to a Si(111) plane that is inclined with respect to the surface of the silicon substrate; then forming an etching protection film on the silicon substrate, the etching protection film protecting the silicon substrate from being etched; then forming an opening corresponding to a second space for the restrictor in the etching pr

Abstract: Provided is a planarizing method in which a planarization with high flatness can be performed, without being restricted by the distribution of film thickness in the applied resist film. The planarizing method comprises the steps of: forming a resist film on a film to be planarized formed on a substrate; exposing the resist film with the amounts of exposure light in respective sections into which an area in which the film to be planarized is formed is divided, the amounts of exposure light being determined so as to realize film thicknesses to be left for planarization of the resist film in the respective sections; developing the exposed resist film, to form a resist film pattern with a controlled distribution of film thickness; and etching the resist film pattern and the film to be planarized, until eliminating the thickness amounts to be eliminated of the film to be planarized.

Abstract: A semiconductor probe with a high-resolution tip and a method of fabricating the same are provided. The semiconductor probe includes: a cantilever doped with a first impurity; a resistive convex portion projecting from an end portion of the cantilever and lightly doped with a second impurity opposite in polarity to the first impurity; and first and second electrode regions formed on either side of the resistive convex portion and heavily doped with the second impurity.

Abstract: A method for manufacturing a probe structure is disclosed. In accordance with the method, two semiconductor substrates having different crystal directions are bonded and selectively etched utilizing an etch selectivity due to the different crystal directions to form a probe tip region and a probe beam region. A cantilever structure for a probe card is formed by filling the probe tip region and the probe beam region with a conductive material.

Abstract: Compositions for lapping gears and methods for preparing the same are described. These compositions contain a salt of polyaspartic acid and may contain additional components that are useful for lapping gears. Also provided are processes for using the compositions described herein.

Abstract: Semiconductor fabrication processes are provided for removing sidewall spacers from gate structures while mitigating or otherwise preventing defect mechanisms such as damage to metal silicide structures or otherwise impeding or placing limitations on subsequent process flows.

Abstract: The invention includes optical signal conduits having rare earth elements incorporated therein. The optical signal conduits can, for example, contain rare earth elements incorporated within a dielectric material matrix. For instance, erbium or cerium can be within silicon nanocrystals dispersed throughout dielectric material of optical signal conduits. The dielectric material can define a path for the optical signal, and can be wrapped in a sheath which aids in keeping the optical signal along the path. The sheath can include any suitable barrier material, and can, for example, contain one or more metallic materials. The invention also includes methods of forming optical signal conduits, with some of such methods being methods in which the optical signal conduits are formed to be part of semiconductor constructions.

Abstract: A micro-fluid ejection device structure and method therefor having improved low energy design. The devices includes a semiconductor substrate and an insulating layer deposited on the semiconductor substrate. A plurality of heater resistors are formed on the insulating layer from a resistive layer selected from the group consisting of TaAl, Ta2N, TaAl(O,N), TaAlSi, Ti(N,O), WSi(O,N), TaAlN, and TaAl/TaAlN. A sacrificial layer selected from an oxidizable metal and having a thickness ranging from about 500 to about 5000 Angstroms is deposited on the plurality of heater resistors. Electrodes are formed on the sacrificial layer from a first metal conductive layer to provide anode and cathode connections to the plurality of heater resistors. The sacrificial layer is oxidized in a plasma oxidation process to provide a fluid contact layer on the plurality of heater resistors.