Patents Examined by Stephanie Duclair
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Patent number: 8969216Abstract: A method for single side texturing of a crystalline semiconductor substrate (10) comprises: providing a substrate (10), for example a semiconductor substrate, comprising a first surface (12) and a second surface (14) opposite to one another with respect to the substrate (10); providing a masking layer (21) with a random pattern on the first surface (12) of the substrate (10); and etching the substrate (10) in a polishing solution, thereby texturing the first surface (12) of the substrate (10) and polishing the second surface (14) in a single wet etching step.Type: GrantFiled: February 11, 2011Date of Patent: March 3, 2015Assignees: IMEC, Katholieke Universiteit Leuven, K.U. Leuven R&DInventors: Victor Prajapati, Joachim John
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Patent number: 8969204Abstract: The present invention relates to a CMP slurry that is able to reduce dishing generation, when it is applied to polishing or planarization of silicon oxide layer, for example, and a polishing method. The CMP slurry includes a polishing abrasive, a linear anionic polymer, a compound including a phosphoric acid group, and water, and the ratio of CMP polishing speed to a silicon oxide layer: CMP polishing speed to a silicon nitride layer is 30:1 to 50:1.Type: GrantFiled: March 3, 2009Date of Patent: March 3, 2015Assignee: LG Chem, Ltd.Inventors: Jong-Pil Kim, Seung-Beom Cho, Jun-Seok Noh, Jang-Yul Kim
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Patent number: 8968583Abstract: A method for cleaning a dielectric and metal structure within a microelectronic structure uses an oxygen containing plasma treatment, followed by an alcohol treatment, in turn followed by an aqueous organic acid treatment. Another method for cleaning a dielectric and metal structure within a microelectronic structure uses an aqueous surfactant treatment followed by an alcohol treatment and finally followed by an aqueous organic acid treatment. The former method may be used to clean a plasma etch residue from a dual damascene aperture. The second method may be used to clean a chemical mechanical polish planarizing residue from a dual damascene structure. The two methods may be used sequentially, absent any intervening or subsequent sputtering method, to provide a dual damascene structure within a microelectronic structure.Type: GrantFiled: July 25, 2007Date of Patent: March 3, 2015Assignee: International Business Machines CorporationInventors: Mary Beth Rothwell, Roy Rongqing Yu
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Patent number: 8968582Abstract: A method of forming an electrode is disclosed. A carbon nanotube is deposited on a substrate. A section of the carbon nanotube is removed to form at least one exposed end defining a first gap. A metal is deposited at the at least one exposed end to form the electrode that defines a second gap.Type: GrantFiled: November 12, 2012Date of Patent: March 3, 2015Assignee: International Business Machines CorporationInventors: Aaron D. Franklin, Joshua T. Smith, George S. Tulevski
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Patent number: 8852448Abstract: A method for fabricating a 3D (three-dimensional) structure is disclosed to provide hydrophobicity to a surface of a 3D structure by using a dipping method in which a predetermined-shaped structure is immersed in a molten metal solution. The method includes: immersing a predetermined-shaped structure in a molten metal solution to coat a molten metal material on the surface of the predetermined-shaped structure; anodizing a metal base coated with the molten metal material; coating a polymer material on an outer surface of the metal-coated base to form a negative replica structure; covering an outer surface of the negative replica structure with an outer formation material; and removing the metal-coated base from the negative replica structure and the outer formation material.Type: GrantFiled: March 12, 2009Date of Patent: October 7, 2014Assignee: Postech Academy-Industry FoundationInventors: Dong-Seob Kim, Kun-Hong Lee, Woon-Bong Hwang, Geun-Bae Lim, Hyun-Chul Park, Byeong-Joo Lee, Sang-Min Lee, Joon-Won Kim
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Patent number: 8846533Abstract: A cleaning solution of the present invention contains a sodium ion, a potassium ion, an iron ion, an ammonium salt of a sulfuric ester represented by General Formula (1), and water, and each content of the sodium ion, the potassium ion, and the iron ion is 1 ppb to 500 ppb. ROSO3—(X)+ (1) where R is an alkyl group with a carbon number of 8-22 or an alkenyl group with a carbon number of 8-22, and (X)+ is an ammonium ion.Type: GrantFiled: May 18, 2009Date of Patent: September 30, 2014Assignee: Kao CorporationInventor: Youichi Ishibashi
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Patent number: 8834729Abstract: A method for making a printed wiring member including wire-bondable contact pads and wear-resistant connector pads, the method includes the steps of a) providing a blank printed wiring member comprising a copper foil laminated to a dielectric substrate; b) masking the blank printed wiring member to protect regions of the copper foil; c) removing copper in unprotected regions of the blank printed wiring member to form a patterned printed wiring member including contact pads and connector pads; d) depositing a nickel coating on the patterned printed wiring member using an electroless nickel deposition process; e) depositing a gold layer on the nickel coating using an electroless gold deposition process; and f) depositing palladium on the gold layer using an electroless palladium deposition process to improve wear resistance of the connector pads while preserving bondability of the contact pads.Type: GrantFiled: November 30, 2009Date of Patent: September 16, 2014Assignee: Eastman Kodak CompanyInventors: Samuel Chen, Charles I. Levey
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Patent number: 8821751Abstract: A CMP composition and associated method are provided that afford good corrosion protection and low defectivity levels both during and subsequent to CMP processing. This composition and method are useful in CMP (chemical mechanical planarization) processing in semiconductor manufacture involving removal of metal(s) and/or barrier layer material(s) and especially for CMP processing in low technology node applications.Type: GrantFiled: June 7, 2011Date of Patent: September 2, 2014Assignee: Air Products and Chemicals, Inc.Inventors: Xiaobo Shi, Ronald Martin Pearlstein
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Patent number: 8822346Abstract: A reaction block having a plurality of reaction chambers defined therein is provided. A bottom surface of each of the reaction chambers is configured to provide a seal for a corresponding reaction region on the substrate and around a periphery of the substrate. The reaction block includes a plurality of inlet channels and provides a gap between a top surface of the substrate and a bottom surface of the reaction block. The gap accepts a fluid from the inlet channels, wherein the reaction block includes a plurality of vacuum channels having access to the bottom surface of the reaction block to remove the fluid from the gap. A method of selectively etching a substrate for combinatorial processing is also provided.Type: GrantFiled: June 10, 2008Date of Patent: September 2, 2014Assignee: Intermolecular, Inc.Inventor: Kurt Weiner
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Patent number: 8815108Abstract: A method of depositing a non-continuous coating of a first material on a substrate, comprising: a) the formation of a mask on this substrate, by forming at least two mask layers, and etching of at least one cavity in these layers, this cavity having an outline such that a coating, deposited on the substrate, through the cavities of the mask, has at least one discontinuity over said outline of the cavity; b) the deposition of the first material on the substrate, through the cavities of the mask, the coating thus deposited having at least one discontinuity over the outline of said cavity; and c) the mask is removed.Type: GrantFiled: April 3, 2008Date of Patent: August 26, 2014Assignee: Commissariat a l'Energie AtomiqueInventors: Bruno Remiat, Laurent Vandroux, Florent Souche
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Patent number: 8796157Abstract: Method of selectively etching a first material on a substrate with a high selectivity towards a second material by flowing a liquid etchant across a substrate surface at a flow sufficiently fast to generate a minimum mean velocity parallel to the substrate's surface, wherein the first material is selected from a group including materials with semiconducting properties based on at least two different chemical elements.Type: GrantFiled: September 1, 2005Date of Patent: August 5, 2014Assignee: Lam Research AGInventor: Gerald Wagner
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Patent number: 8790527Abstract: A method for providing waveguide structures for an energy assisted magnetic recording (EAMR) transducer is described. The waveguide structures have a plurality of widths. At least one waveguide layer is provided. Mask structure(s) corresponding to the waveguide structures and having a pattern are provided on the waveguide layer(s). The mask structure(s) include a planarization stop layer, a planarization assist layer on the planarization stop layer, and a hard mask layer on the planarization assist layer. The planarization assist layer has a low density. The pattern of the mask structure(s) is transferred to the waveguide layer(s). Optical material(s) that cover the waveguide layer(s) and a remaining portion of the mask structure(s) are provided. The optical material(s) have a density that is at least twice the low density of the planarization assist layer. The method also includes performing a planarization configured to remove at least a portion of the optical material(s).Type: GrantFiled: March 22, 2011Date of Patent: July 29, 2014Assignee: Western Digital (Fremont), LLCInventors: Guanghong Luo, Ming Jiang, Danning Yang, Yunfei Li
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Patent number: 8778802Abstract: A polishing method includes causing a polishing pad arranged on a turn table to rotate together with the turn table, and polishing a surface of a substrate by using the rotating polishing pad while supplying a chemical fluid to a surface of the polishing pad on a fore side of the substrate from an oblique direction with respect to the surface of the polishing pad.Type: GrantFiled: May 23, 2007Date of Patent: July 15, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Dai Fukushima, Gaku Minamihaba, Hiroyuki Yano
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Patent number: 8778205Abstract: The present invention is a processing method including a processing step of performing predetermined processing for a workpiece; an unnecessary portion removal step of removing an unnecessary portion produced on a surface of the workpiece due to the predetermined processing; and a surface structure evaluation step of evaluating a surface structure of the workpiece from which the unnecessary portion has been removed by the unnecessary portion removal step.Type: GrantFiled: October 14, 2009Date of Patent: July 15, 2014Assignee: Tokyo Electron LimitedInventors: Tsuyoshi Ohno, Toshihiko Kikuchi, Machi Moriya, Yoshitaka Saita
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Patent number: 8778211Abstract: The present invention provides chemical-mechanical polishing (CMP) compositions suitable for polishing a substrate comprising a germanium-antimony-tellurium (GST) alloy. The CMP compositions of the present invention are aqueous slurries comprising a particulate abrasive, a water-soluble surface active agent, a complexing agent, and a corrosion inhibitor. The ionic character of the surface active material (e.g., cationic, anionic, or nonionic) is selected based on the zeta potential of the particulate abrasive. A CMP method for polishing a GST alloy-containing substrate utilizing the composition is also disclosed.Type: GrantFiled: July 17, 2012Date of Patent: July 15, 2014Assignee: Cabot Microelectronics CorporationInventors: Matthias Stender, Glenn Whitener, Chul Woo Nam
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Patent number: 8764997Abstract: A method of metal deposition may include chemically modifying a surface of a substrate to make the surface hydrophobic. The method may further include depositing a layer of metal over the hydrophobic surface and masking at least a portion of the deposited metal layer to define a conductive metal structure. The method may also include using an etching agent to etch unmasked portions of the deposited metal layer.Type: GrantFiled: July 13, 2010Date of Patent: July 1, 2014Assignee: STMicroelectronics S.R.L.Inventors: Fabrizio Porro, Luigi Giuseppe Occhipinti
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Patent number: 8709954Abstract: A wafer recycling method comprises varying a temperature and pressure conditions to remove a first semiconductor layer deposited on a wafer, removing a remaining semiconductor layer on the wafer through a chemical or physical process, and washing the wafer.Type: GrantFiled: June 23, 2008Date of Patent: April 29, 2014Assignee: LG Innotek Co., Ltd.Inventors: Kyung Jun Kim, Hyo Kun Son
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Patent number: 8703617Abstract: The present application discloses provides a method for planarizing an interlayer dielectric layer, comprising the steps of: providing a multilayer structure including at least one sacrificial layer and at least one insulating layer under the sacrificial layer on the semiconductor substrate and the first gate stack, performing a first RIE on the multilayer structure, in which a reaction chamber pressure is controlled in such a manner that an etching rate of the portion of the at least one sacrificial layer at a center of a wafer is higher than that at an edge of the wafer, so as to obtain a concave etching profile; performing a second RIE on the multilayer structure to completely remove the sacrificial layer and a part of the insulating layer, so as to obtain the insulating layer having a planar surface which serves as an interlayer dielectric layer.Type: GrantFiled: February 17, 2011Date of Patent: April 22, 2014Assignee: Institute of Microelectronics, Chinese Academy of SciencesInventors: Huaxiang Yin, Qiuxia Xu, Lingkuan Meng, Tao Yang, Dapeng Chen
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Patent number: 8685266Abstract: Monocyclic chlorine based inductively coupled plasma deep etching processes for the rapid micromachining of titanium substrates and titanium devices so produced are disclosed. The method parameters are adjustable to simultaneously vary etch rate, mask selectivity, and surface roughness and can be applied to titanium substrates having a wide variety of thicknesses to produce high aspect ratio features, smooth sidewalls, and smooth surfaces. The titanium microdevices so produced exhibit beneficially high fracture toughness, biocompatibility and are robust and able to withstand harsh environments making them useful in a wide variety of applications including microelectronics, micromechanical devices, MEMS, and biological devices that may be used in vivo.Type: GrantFiled: October 2, 2006Date of Patent: April 1, 2014Assignee: The Regents of the University of CaliforniaInventors: Emily R. Parker, Brian J. Thibeault, Marco F. Aimi, Masa P. Rao, Noel C. MacDonald
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Patent number: 8641916Abstract: A plasma etching method for forming a hole in an etching target film by a plasma processing apparatus is provided. The apparatus includes an RF power supply for applying RF power for plasma generation to at least one of upper and lower electrodes, and a DC power supply for applying minus DC voltage to the upper electrode. A first condition that plasma is generated by turning on the RF power supply and minus DC voltage is applied to the upper electrode and a second condition that the plasma is extinguished by turning off the RF power supply and minus DC voltage is applied to the upper electrode are alternately repeated. Etching is performed by positive ions in the plasma under the first condition and negative ions are supplied into the hole by the DC voltage to neutralize positive ions in the hole under the second condition.Type: GrantFiled: January 25, 2010Date of Patent: February 4, 2014Assignee: Tokyo Electron LimitedInventors: Koichi Yatsuda, Yoshinobu Ooya, Shin Okamoto, Hiromasa Mochiki