Patents Examined by Stephanie Duclair
  • Patent number: 9779952
    Abstract: Techniques herein include methods for controllable lateral etching of dielectrics in polymerizing fluorocarbon plasmas. Methods can include dielectric stack etching that uses a mask trimming step as part of a silicon etching process. Using a fluorocarbon mixture for dielectric mask trimming provides several advantages, such as being straightforward to apply and providing additional flexibility to the process flow. Thus, techniques herein provide a method to correct or tune CDs on a hardmask. In general, this technique can include using a fluorine-based and a fluorocarbon-based, or fluorohydrocarbon-based, chemistry for creating a plasma, and controlling a ratio of the two chemistries. Without the hardmask trim method disclosed herein, if a hardmask CD is not on target, then a wafer is scrapped. With hard-mask trim capability in silicon etch as disclosed herein, a given CD can be re-targeted to eliminate wafer-scraps.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: October 3, 2017
    Assignee: Tokyo Electron Limited
    Inventors: Alok Ranjan, Sergey Voronin
  • Patent number: 9779961
    Abstract: Disclosed is a method for etching a first region including a multi-layer film formed by providing silicon oxide films and silicon nitride films alternately, and a second region having a single silicon oxide film. The etching method includes: providing a processing target object including a mask provided on the first region and the second region within a processing container of a plasma processing apparatus; generating plasma of a first processing gas including a hydrofluorocarbon gas within the processing container that accommodates the processing target object; and generating plasma of a second processing gas including a fluorocarbon gas within the processing container that accommodates the processing target object. The step of generating the plasma of the first processing gas and the step of generating the plasma of the second processing gas are alternately repeated.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: October 3, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yusuke Saitoh, Yu Nagatomo, Hayato Hishinuma, Wataru Takayama, Sho Tominaga, Yuki Kaneko
  • Patent number: 9773679
    Abstract: Disclosed are sulfur-containing compounds for plasma etching channel holes, gate trenches, staircase contacts, capacitor holes, contact holes, etc., in Si-containing layers on a substrate and plasma etching methods of using the same. The plasma etching compounds may provide improved selectivity between the Si-containing layers and mask material, less damage to channel region, a straight vertical profile, and reduced bowing in pattern high aspect ratio structures.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: September 26, 2017
    Assignee: American Air Liquide, Inc.
    Inventors: Rahul Gupta, Venkateswara R. Pallem, Vijay Surla, Curtis Anderson, Nathan Stafford
  • Patent number: 9774714
    Abstract: A method for fabricating a window member is provided. A transparent substrate including a transmitting region and a non-transmitting region may be prepared. A light curable adhesive layer may be disposed on the transparent substrate. A plurality of micro patterns may be disposed on the transparent substrate or the light curable adhesive layer in the non-transmitting region. The light curable adhesive layer may be cured by light irradiation. The light curable adhesive layer may include a transparent adhesive. A storage modulus of the transparent adhesive may be greater than or equal to about 103 Pa and less than about 106 Pa at room temperature before curing, and greater than or equal to about 106 Pa at room temperature after curing.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: September 26, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jong-Whan Cho, Hyeon-Deuk Hwang, Jong-Deok Park
  • Patent number: 9758697
    Abstract: The invention provides chemical-mechanical polishing compositions and methods of chemically-mechanically polishing a substrate, especially a substrate comprising a silicon oxide layer, with the chemical-mechanical polishing compositions. The polishing compositions comprise first abrasive particles, wherein the first abrasive particles are wet-process ceria particles, have a median particle size of about 75 nm to about 200 nm, and are present in the polishing composition at a concentration of about 0.005 wt. % to about 2 wt. % a functionalized heterocycle, a cationic polymer selected from a quaternary amine, is cationic polyvinyl alcohol, and a cationic cellulose, optionally a carboxylic acid, a pH-adjusting agent, and an aqueous carrier, and have a pH of about 1 to about 6.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: September 12, 2017
    Assignee: Cabot Microelectronics Corporation
    Inventors: Brian Reiss, Dana Sauter Van Ness, Viet Lam, Renhe Jia
  • Patent number: 9758876
    Abstract: A method for forming a plurality of precision holes in a substrate by drilling, including affixing a sacrificial cover layer to a surface of the substrate, positioning a laser beam in a predetermined location relative to the substrate and corresponding to a desired location of one of the plurality of precision holes, forming a through hole in the sacrificial cover layer by repeatedly pulsing a laser beam at the predetermined location, and pulsing the laser beam into the through hole formed in the sacrificial cover layer. A work piece having precision holes including a substrate having the precision holes formed therein, wherein a longitudinal axis of each precision hole extends in a thickness direction of the substrate, and a sacrificial cover layer detachably affixed to a surface of the substrate, such that the sacrificial cover layer reduces irregularities of the precision holes.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: September 12, 2017
    Assignee: CORNING INCORPORATED
    Inventors: Aric Bruce Shorey, Garrett Andrew Piech, Xinghua Li, John Christopher Thomas, John Tyler Keech, Jeffrey John Domey, Paul John Shustack
  • Patent number: 9754800
    Abstract: A method of etching patterned heterogeneous silicon-containing structures is described and includes a remote plasma etch with inverted selectivity compared to existing remote plasma etches. The methods may be used to conformally trim polysilicon while removing little or no silicon oxide. More generally, silicon-containing films containing less oxygen are removed more rapidly than silicon-containing films which contain more oxygen. Other exemplary applications include trimming silicon carbon nitride films while essentially retaining silicon oxycarbide. Applications such as these are enabled by the methods presented herein and enable new process flows. These process flows are expected to become desirable for a variety of finer linewidth structures. Methods contained herein may also be used to etch silicon-containing films faster than nitrogen-and-silicon containing films having a greater concentration of nitrogen.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: September 5, 2017
    Assignee: Applied Materials, Inc.
    Inventors: Jingchun Zhang, Anchuan Wang, Nitin K. Ingle
  • Patent number: 9752074
    Abstract: A pickling solution for the surface pre-treatment of plastic surfaces in preparation for metallization, the solution comprising a source of Mn(VII) ions; and an inorganic acid; wherein the pickling solution is substantially free of chromium (VI) ions, alkali ions, and alkaline-earth ions.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: September 5, 2017
    Inventors: Mark Peter Schildmann, Ulrich Prinz, Christoph Werner
  • Patent number: 9735069
    Abstract: A method for dry processing a substrate in a processing chamber is provided. The substrate is placed in the processing chamber. The substrate is dry processed, wherein the dry processing creates at least one gas byproduct. A concentration of the at least one gas byproduct is measured. The concentration of the at least one gas byproduct is used to determine processing rate of the substrate.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: August 15, 2017
    Assignee: Lam Research Corporation
    Inventors: Yassine Kabouzi, Luc Albarede, Andrew D. Bailey, III, Jorge Luque, Seonkyung Lee, Thorsten Lill
  • Patent number: 9735021
    Abstract: An etching method of etching a first region including a multilayered film, in which silicon oxide films and silicon nitride films are alternately stacked, and a second region including a single-layered silicon oxide film is provided. The etching method includes a first plasma process of generating plasma of a first processing gas containing a fluorocarbon gas and an oxygen gas within a processing vessel of a plasma processing apparatus; and a second plasma process of generating plasma of a second processing gas containing a hydrogen gas, nitrogen trifluoride gas, a hydrogen bromide gas and a carbon-containing gas within the processing vessel. A temperature of an electrostatic chuck is set to a first temperature in the first plasma process, and the temperature of the electrostatic chuck is set to a second temperature lower than the first temperature in the second plasma process.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: August 15, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Masayuki Sawataishi, Tomonori Miwa
  • Patent number: 9728417
    Abstract: An exemplary embodiment provides a method which etches a second layer in a base body to be processed having a first layer containing Ni and Si and a second layer containing Si and N which are exposed to a surface thereof. The method according to the exemplary embodiment includes (a) preparing a base body to be processed in a processing chamber, and (b) supplying a first processing gas which contains carbon and fluorine but does not contain oxygen into the processing chamber and generating plasma in the processing chamber.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: August 8, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Masaki Inoue, Toshihisa Ozu, Takehiro Tanikawa, Jun Yoshikawa
  • Patent number: 9721803
    Abstract: In one embodiment of the present invention, an etching method for a substrate to be processed comprises: (a1) a step in which etchant gas is supplied into a processing container than accommodates a substrate to be processed; (b1) a step in which the inside of the processing container is evacuated; (c1) a step in which a noble gas is supplied into the processing container; and (d1) a step in which microwaves are supplied into the processing container so as to excite the plasma of the noble gas inside the processing container. The sequential process including the step of supplying the etchant of supplying the etchant gas, the evacuating step, the step of supplying the noble gas, and the step of exciting the plasma of the noble gas may be repeated.
    Type: Grant
    Filed: April 10, 2013
    Date of Patent: August 1, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Hiroyuki Takaba
  • Patent number: 9716011
    Abstract: A method of manufacturing a semiconductor device, the method, comprising a first etching step of etching a substrate on which a silicon member and a compound member containing nitrogen and silicon are exposed, by using a first etching gas containing XeF2 and H2, and a second etching step of etching the substrate by using a second etching gas containing XeF2, wherein the second etching gas satisfies at least one of (i) a condition that the second etching gas is lower in a partial pressure of H2 than the first etching gas, and (ii) a condition that the second etching gas is smaller in a quantity of flow of H2 than the first etching gas.
    Type: Grant
    Filed: January 6, 2015
    Date of Patent: July 25, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Masaaki Minowa, Takayuki Sumida
  • Patent number: 9711359
    Abstract: A method for etching an etch layer in a stack over a substrate wherein the etch layer is under a mask layer which is under a patterned organic mask is provided. The stack and substrate is placed on a support in the plasma chamber. A silicon based layer is deposited in situ over the stack. The silicon based layer is etched to form silicon based sidewalls or spacers on sides of the patterned organic mask. The mask layer is selectively etched with respect to the silicon based sidewalls or spacers, wherein the selectively etching the mask layer undercuts the silicon based sidewalls or spacers. The etch layer is selectively etched with respect to the mask layer. The stack and substrate are removed from the support and the plasma chamber.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: July 18, 2017
    Assignee: Lam Research Corporation
    Inventors: Tom A. Kamp, Rodolfo P. Belen, Jr.
  • Patent number: 9711365
    Abstract: Pretreatment of an etch chamber for performing a silicon etch process and Bosch process can be effected by running a deposition process employing C5HF7, or by running an alternating deposition and etch process employing C5H2F6 and SF6. It has been discovered that the pretreatment of the etch chamber for the silicon etch process can enhance the etch rate of silicon by at least 50% without adverse effect on etch profile during a first each process following the pretreatment, while the etch rate enhancement factor decreases over time. By periodically performing the pretreatment in the etch chamber, the throughput of the etch chamber can be increased without adversely impacting the etch profile of the processed substrates.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: July 18, 2017
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, ZEON CORPORATION
    Inventors: Eric A. Joseph, Goh Matsuura, Masahiro Nakamura, Edmund M. Sikorski, Bang N. To
  • Patent number: 9695506
    Abstract: The disclosure relates to a method of making a microstructure on a substrate. A carbon nanotube structure is provided, wherein the carbon nanotube structure includes a number of carbon nanotubes arranged orderly and defines a number of first openings. A carbon nanotube composite is formed by applying a protective layer on the carbon nanotube structure, wherein the carbon nanotube composite structure defines a number of second openings. The carbon nanotube composite structure is placed on a surface of the substrate, wherein parts of the surface are exposed from the number of second openings. The surface of the substrate is dry etched by using the carbon nanotube composite structure as a mask.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: July 4, 2017
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yuan-Hao Jin, Qun-Qing Li, Shou-Shan Fan
  • Patent number: 9690192
    Abstract: A composition for a base of a directed self-assembling film includes a compound including an oxo acid group, and a solvent. The compound is preferably represented by formula (1). A represents an organic group having 10 or more carbon atoms and having a valency of n. B represents an oxo acid group. n is an integer of 1 to 200. In a case where n is 2 or greater, a plurality of Bs are identical or different.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: June 27, 2017
    Assignee: JSR CORPORATION
    Inventors: Hiroyuki Komatsu, Takehiko Naruoka, Shinya Minegishi, Kaori Sakai, Tomoki Nagai
  • Patent number: 9685316
    Abstract: A semiconductor process includes the following steps. A wafer on a pedestal is provided. The pedestal is lifted to approach a heating source and an etching process is performed on the wafer. An annealing process is performed on the wafer by the heating source. In another way, a wafer on a pedestal, and a heating source on a same side of the wafer as the pedestal are provided. An etching process is performed on the wafer by setting the temperature difference between the heating source and the pedestal larger than 180° C.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: June 20, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia Chang Hsu, Kuo-Chih Lai, Chun-Ling Lin, Bor-Shyang Liao, Pin-Hong Chen, Shu Min Huang, Min-Chung Cheng, Chi-Mao Hsu
  • Patent number: 9673057
    Abstract: A method for forming a stair-step structure in a substrate within a plasma processing chamber is provided. An organic mask is formed over the substrate. The organic mask is trimmed with a vertical to lateral ratio of less than 0.8, wherein the trimming simultaneously forms a deposition over the organic mask. The substrate is etched. The steps of trimming the organic mask and etching the substrate are cyclically repeated a plurality of times.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: June 6, 2017
    Assignee: Lam Research Corporation
    Inventors: In Deog Bae, Qian Fu
  • Patent number: 9659791
    Abstract: Methods are described for etching metal layers that are difficult to volatize, such as cobalt, nickel, and platinum to form an etched metal layer with reduced surface roughness. The methods include pretreating the metal layer with a local plasma formed from a hydrogen-containing precursor. The pretreated metal layer is then reacted with a halogen-containing precursor to form a halogenated metal layer having a halogenated etch product. A carbon-and-nitrogen-containing precursor reacts with the halogenated etch product to form a volatile etch product that can be removed in the gas phase from the etched surface of the metal layer. The surface roughness may be reduced by performing one or more plasma treatments on the etching metal layer after a plurality of etching sequences. Surface roughness is also reduced by controlling the temperature and length of time the metal layer is reacting with the etchant precursors.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: May 23, 2017
    Assignee: Applied Materials, Inc.
    Inventors: Xikun Wang, David Cui, Anchuan Wang, Nitin K. Ingle