Abstract: Providing memory bandwidth compression using compressed memory controllers (CMCs) in a central processing unit (CPU)-based system is disclosed. In this regard, in some aspects, a CMC is configured to receive a memory read request to a physical address in a system memory, and read a compression indicator (CI) for the physical address from a master directory and/or from error correcting code (ECC) bits of the physical address. Based on the CI, the CMC determines a number of memory blocks to be read for the memory read request, and reads the determined number of memory blocks. In some aspects, a CMC is configured to receive a memory write request to a physical address in the system memory, and generate a CI for write data based on a compression pattern of the write data. The CMC updates the master directory and/or the ECC bits of the physical address with the generated CI.

Abstract: A system and related method for optimizing warm-start loading in a multi-core processing environment (MCPE) responds to a power transient event. The MCPE system memory activates a self-refresh mode, maintaining stored data throughout the power event. A boot loader in nonvolatile flash memory identifies the warm-start condition and fetches from the flash memory the hypervisor binary image. Rather than copy the entire image to allocated system memory, the boot loader copies only the modifiable portions of the hypervisor image, transferring control to the hypervisor. The hypervisor spawns guest processes that copy guest OS and application images from flash memory, copying only the modifiable portions of these images to the appropriate destinations in allocated memory before transferring control to the guest processes. By loading only modifiable image segments and sections, the system reduces the time required for the warm-start sequence.

Abstract: Example embodiments of the present invention relate and a method and an apparatus for managing a short hash handle. The method including receiving an I/O including a first identifier for a data block and examining the first identifier in comparison with a second identifier. The data block identified in the I/O then may be managed according to the first identifier and the second identifier.

Abstract: A data storage device may be configured to update a table used by a host device, such as a table stored at the data storage device. For, example, the data storage device may generate and store an updated version of a portion of the table. A storage location of the updated version of the portion may be tracked using a data structure that corresponds to a second version of the table. The second version of the table may be discarded or made accessible to the host device responsive to an indicator detected by the data storage device.

Abstract: A computer system includes transactional memory to implement a nested transaction. The computer system generates a plurality of speculative identification numbers (IDs), identifies at least one of a software thread executed by a hardware processor and a memory operation performed in accordance with an application code. The computer system assigns at least one speculative cache version to a requested transaction based on a corresponding software thread. The speculative ID of the corresponding software thread identifies the speculative cache version. The computer system also identifies a nested transaction in the memory unit, assigns a cache version to the nested transaction, detects a conflict with the nested transaction, determines a conflicted nesting level of the nested transaction, and determines a cache version corresponding to the conflicted nesting level. The computer system also invalidates the cache version corresponding to the conflicted nesting level.

Abstract: Described embodiments provide systems and processes for performing data replication in a storage system. The data replication operation replicates data from at least one source device to at least one target device of the storage system. A link capacity of a link between at least one source device and at least one target device is determined. Processor overhead associated with one or more data compression processes, and one or more operating conditions of the storage system are determined. Based at least at least in part upon the determined link capacity, the determined processor overhead, and the determined one or more operating conditions, one or more settings of a data replication operation of the storage system are adapted. The data replication operation is performed according to the adapted one or more settings.

Abstract: In general, techniques are described for enabling performance tuning of a storage device. A storage device comprising one or more processors and a memory may perform the tuning techniques. The one or more processors may be configured to receive a command stream including one or more commands to access the storage device. The memory may be configured to store the command stream. The one or more processors may be further configured to insert a delay into the command stream to generate a performance tuned command stream, and access the storage device in accordance with the performance tuned command stream.

Abstract: A processor includes a first memory interface to be coupled to a plurality of dual in-line memory module (DIMM) sockets located off-package, a second memory interface to be coupled to a non-volatile memory (NVM) socket located off-package, and a multi-level memory controller (MLMC). The MLMC is to: control the DIMMs disposed in the plurality of DIMM sockets as main memory in a one-level memory (1LM) configuration; detect a switch from a 1LM mode of operation to a two-level memory (2LM) mode of operation in response to a basic input/output system (BIOS) detection of a low-power DIMM disposed in one of the DIMM sockets and a NVM device disposed in the NVM socket in a 2LM configuration; and control the low-power DIMM as cache in the 2LM configuration in response to detection of the switch from the 1LM mode of operation to the 2LM mode of operation.

Abstract: A computer system includes transactional memory to implement a nested transaction. The computer system generates a plurality of speculative identification numbers (IDs), identifies at least one of a software thread executed by a hardware processor and a memory operation performed in accordance with an application code. The computer system assigns at least one speculative cache version to a requested transaction based on a corresponding software thread. The speculative ID of the corresponding software thread identifies the speculative cache version. The computer system also identifies a nested transaction in the memory unit, assigns a cache version to the nested transaction, detects a conflict with the nested transaction, determines a conflicted nesting level of the nested transaction, and determines a cache version corresponding to the conflicted nesting level. The computer system also invalidates the cache version corresponding to the conflicted nesting level.

Abstract: Apparatuses, computer readable mediums, and methods of processor unit testing using cache resident testing are disclosed. The method may include loading a test program in a cache on a chip comprising one or more processor units. The method may include the one or more processor units executing the test program to generate one or more results. The method may include redirecting a first memory reference to the cache, wherein the first memory reference is generated during the execution of the test program. The method may include determining whether the one or more generated results match one or more test results. The method may include redirecting a memory request to a memory location resident in the cache if the memory request includes a memory location not resident in the cache. The method may include redirecting a memory request to the cache if the memory request is not directed to the cache.

Abstract: Aspects of the present disclosure disclose systems and methods for managing space in storage devices. In various aspects, the disclosure is directed to providing more efficient method for managing free space in the storage system, and related apparatus and methods. In particular, the system provides for freeing blocks of memory that are no longer being used based on the information stored in a file system. More specifically, the system allows for reclaiming of large segments of free blocks at one time by providing information on aggregated blocks that were being freed to the storage devices.

Abstract: Methods, apparatus and computer program products implement embodiments of the present invention that include storing one or more data volumes to a small computer system interface storage device, and receiving a request to map a given data volume to a host computer. One or more attributes of the given data volume are identified, and using the identified one or more attributes, a unique logical unit number (LUN) for the given data volume is generated. The given data volume is mapped to the host computer via the unique LUN. In some embodiments, the generated LUN includes one of the one or more attributes. In additional embodiments, the generated LUN includes a result of a hash function using the one or more attributes. In storage virtualization environments, the data volume may include secondary logical units, and mapping the given data volume to the host may include binding the SLU to the host.

Abstract: Methods and system for providing a security function, such as random number generation, fingerprinting and data hiding, using a Flash memory. The methods and systems do not require carefully design specific circuits, can be implemented in all flash memory device. The fingerprinting methods and systems do not require a long time to generate a read and the data hiding is decoupled from Flash memory content.

Abstract: In one aspect, a method includes splitting empty RAID stripes into sub-stripes and storing pages into the sub-stripes based on a compressibility score. In another aspect, a method includes reading pages from 1-stripes, storing compressed data in a temporary location, reading multiple stripes, determining compressibility score for each stripe and filling stripes based on the compressibility score. In a further aspect, a method includes scanning a dirty queue in a system cache, compressing pages ready for destaging, combining compressed pages in to one aggregated page, writing one aggregated page to one stripe and storing pages with same compressibility score in a stripe.

Abstract: A storage control apparatus includes a plurality of MBFs for managing pieces of data stored in a storage by storage region, caches some of the MBFs on a RAM, and determines the presence or absence of redundancy on a basis of the MBFs on the RAM alone. The storage control apparatus performs redundancy elimination on the pieces of data already stored in the storage on the basis of how the MBFs are used such that the contents of a hash log for an MBF higher in frequency of use are maintained.

Abstract: Methods, apparatus and computer program products implement embodiments of the present invention that include storing one or more data volumes to a small computer system interface storage device, and receiving a request to map a given data volume to a host computer. One or more attributes of the given data volume are identified, and using the identified one or more attributes, a unique logical unit number (LUN) for the given data volume is generated. The given data volume is mapped to the host computer via the unique LUN. In some embodiments, the generated LUN includes one of the one or more attributes. In additional embodiments, the generated LUN includes a result of a hash function using the one or more attributes. In storage virtualization environments, the data volume may include secondary logical units, and mapping the given data volume to the host may include binding the SLU to the host.

Abstract: A computer system that employs a solid-state memory device as a physical storage resource includes a hypervisor that is capable of supporting TRIM commands issued by virtual machines running in the computer system. When a virtual machine issues a TRIM command to its corresponding virtual storage device to invalidate data stored therein, the TRIM command is received at an interface layer in the hypervisor that translates the TRIM command to a SCSI command known as UMMAP. A SCSI virtualization layer converts the UNMAP command to a file system command to delete portions of the virtual storage device that is maintained as a file in the hypervisor's file system. Upon receiving the delete commands, the hypervisor's file system driver generates a TRIM command to invalidate the data stored in the solid-state memory device at locations corresponding to the portions of the file that are to be deleted.

Abstract: A computer determines an intrinsic read speed and an intrinsic write speed associated with a first disk and a second disk. The computer receives a request to read a portion of data, wherein the portion of data is stored redundantly on both the first and second disk. The computer identifies a first latency associated with reading the portion of data from the first disk, where the first latency is based on at least the intrinsic read speed and the intrinsic write speed associated with the first disk. The computer identifies a second latency associated with reading the portion of data from the second disk, wherein the second latency is based on at least the intrinsic read speed and the intrinsic write speed associated with the second disk. The computer determines that the first latency exceeds the second latency. The computer selects the second disk to read the portion of data.

Abstract: Systems and methods for granular cache repair. An example processing system comprises a processing core communicatively coupled to a cache via a cache controller and a cache repair memory communicatively coupled to the cache controller. The cache controller is configured, responsive to receiving a read request referencing a physical address, to: retrieve cache data from a cache location identified by the physical address, retrieve, in parallel with retrieving the cache data, cache repair data from the cache repair memory, the cache repair data associated with the cache location, the cache repair data comprising at least one of: a bit repair value, a column repair value, and a raw repair value, and output the cache data multiplexed with the cache repair data.

Abstract: A nonvolatile memory device includes a memory cell array, a row decoder, a page buffer, and control logic. The memory cell array includes memory cells connected to word lines and bit lines, the memory cell array being configured to store data. The row decoder is configured to selectively activate a string selection line, a ground selection line, and the word lines of the memory cell array. The page buffer is configured to temporarily store external data and to apply a predetermined voltage to the bit lines according to the stored data during a program operation, and to sense data stored in selected memory cells using the bit lines during a read operation or a verification operation. The control logic is configured to control the row decoder and the page buffer. During execution of commands, when a request to suspend the execution of the commands is retrieved, chip information is backed up to a storage space separate from the control logic.