Abstract: In the present invention, computational efficiency degradation is suppressed when diagnosing a shared storage area in a vehicle control device in which a plurality of computing units are employed. This vehicle control device suppresses computational efficiency degradation by changing an access destination in a storage device while diagnosing a shared storage area that the storage device has.

Abstract: In one aspect, a method includes splitting empty RAID stripes into sub-stripes and storing pages into the sub-stripes based on a compressibility score. In another aspect, a method includes reading pages from 1-stripes, storing compressed data in a temporary location, reading multiple stripes, determining compressibility score for each stripe and filling stripes based on the compressibility score. In a further aspect, a method includes scanning a dirty queue in a system cache, compressing pages ready for destaging, combining compressed pages in to one aggregated page, writing one aggregated page to one stripe and storing pages with same compressibility score in a stripe.

Abstract: Techniques for request processing may include: receiving, at a data storage system, a plurality of requests from one or more clients, wherein the plurality of requests are in accordance with an application programming interface (API); collecting usage information regarding the plurality of requests; and periodically transmitting portions of the usage information to a data center. The usage information may include usage statistics regarding usage aspects of the API with respect to different types or classes of components in the data storage system. The usage information may be further analyzed for any suitable purpose such as to prioritize and identify existing features, services and/or commands for further development and improvement; identify unused or infrequently used features, commands, and/or parameters; and identify potential user interface enhancement.

Abstract: Example embodiments of the present invention relate and a method and an apparatus for double hashing. The method including receiving a hash signature, including a short hash handle, for a data block. The method then includes determining a bucket with which the hash signature should be associated and associating the hash signature with the bucket.

Abstract: Systems and methods for solid-state storage drive-level failure prediction and health metric are described. A plurality of host-write commands are received at a solid-state storage device. A number of drive-writes per day based on the on the plurality of host-write commands is determined. An aggregated amount of degradation to one or more internal non-volatile memory components based on the number of drive-writes per day is determined. Using a machine-learned model, a probability of failure value based on a set of parameter data and the aggregated amount of degradation to the non-volatile memory component is generated. An alert is generated, based on the probability of failure value or degradation threshold.

Abstract: One or more techniques and/or systems are provided for managing configuration updates used to replicate configuration of a primary storage virtual machine to a partner storage virtual machine. For example, the partner storage virtual machine may be configured to provide failover operation in place of the primary storage virtual machine in the event the primary storage virtual machine fails. Configuration updates are queued and replayed on the partner storage virtual machine to replicate objects of the primary storage virtual machine to the partner storage virtual machine (e.g., replay of create, modify, or delete object commands for synchronizing volumes, logical unit numbers, and/or other configuration objects of the primary storage virtual machine to the partner storage virtual machine).

Abstract: In at least some embodiments, a processor core generates a store operation by executing a store instruction in an instruction sequence. The store operation is marked as a high priority store operation in response to the store instruction being marked as high priority and is not so marked otherwise. The store operation is buffered in a store queue associated with a cache memory of the processor core. Handling of the store operation in the store queue is expedited in response to the store operation being marked as a high priority store operation and not expedited otherwise.

Abstract: Novel technology for data object processing may include a system comprising a non-transitory memory; a non-transitory storage device; and a storage logic communicatively coupled to the non-transitory storage device and the non-transitory memory. The storage logic may be executable to perform operations comprising preparing a first log payload in the non-transitory memory; generating a first log bitmap describing a set of states for a set of logical blocks of an erase block of the non-transitory storage device; generating a first log including the first log bitmap and the first log payload; and storing the first log in the erase block of the non-transitory storage device.

Abstract: A memory system include: a plurality of first memory devices each coupled to a first channel and including a plurality of first memory blocks; a plurality of second memory devices each coupled to a second channel and including a plurality of second memory blocks; a first access controller suitable for controlling an access to the first memory blocks; a second access controller suitable for controlling an access to the second memory blocks; and a bad block controller suitable for: selecting one between the first and second access controllers by comparing bad physical addresses corresponding to bad blocks included in each of the first and second memory devices with first and second physical addresses respectively corresponding to the first and second memory blocks, and transferring one of the first and second physical addresses and substitute physical address that replace the bad physical addresses.

Abstract: An apparatus of this invention is directed to a storage control apparatus that improves the access performance of a storage medium and prolongs the life of the storage medium. The storage control apparatus includes a determiner that determines whether to estimate that data at a logical address area in a logical address space used by a host computer to access a storage medium is fragmented and stored in a plurality of physical address areas in a physical address space used in the storage medium, and a data rearrangement unit that reads the fragmented data by designating a logical address area corresponding to the fragmented data which has been estimated to be fragmented and stored in the plurality of physical address areas in the physical address space, and instructs the storage medium to write the read fragmented data in the logical address area while controlling other write operations, so that the fragmented data is written in continuous physical address areas in the storage medium.

Abstract: A data storage system may obtain data, a size of the data, and a data structure type of the data. The system may allocate a memory block for the data based on the size of the data and a predetermined block size. The system may store the data in the allocated memory block. The allocated memory block may include a block attribute that includes the data and a head comprising management information corresponding to the block attribute. The management information may include a first block identifier for an antecedent memory block and a second block identifier for a succeeding memory block. The system may link, based on the data structure type, the allocated memory block to a plurality of memory blocks arranged in at least one of a block list structure or a tree structure.

Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

Abstract: A computer system that employs a solid-state memory device as a physical storage resource includes a hypervisor that is capable of supporting TRIM commands issued by virtual machines running in the computer system. When a virtual machine issues a TRIM command to its corresponding virtual storage device to invalidate data stored therein, the TRIM command is received at an interface layer in the hypervisor that translates the TRIM command to a SCSI command known as UMMAP. A SCSI virtualization layer converts the UNMAP command to a file system command to delete portions of the virtual storage device that is maintained as a file in the hypervisor's file system. Upon receiving the delete commands, the hypervisor's file system driver generates a TRIM command to invalidate the data stored in the solid-state memory device at locations corresponding to the portions of the file that are to be deleted.

Abstract: A memory system may include a volatile memory that is configured to store an address data structure that includes a plurality of logical-to-physical address entries. The address data structure may be stored across a plurality of bank groups of the volatile memory. A controller may be configured to store consecutive logical-to-physical address entries across different bank groups. In turn, during read and write operations for data sets associated with consecutive logical addresses, read requests for physical addresses where the data sets are stored may be sent to multiple bank groups and processed by the multiple banks in parallel.

Abstract: A computer-executable method, system, and computer program product for processing data on a data storage system including a primary data storage system and a secondary data storage system, the computer-executable method, system, and computer program product comprising replicating the primary data storage system on the secondary data storage system, processing a mapping of the data on the primary data storage system, wherein a result of the mapping is replicated on the secondary data storage system, and processing a portion of reducing of the data on the secondary data storage system.

Abstract: A query is received in a session established between an application and an in-memory database. The query is received from the application. Based on one or more criteria defined for individual data aging parameters in the data aging infrastructure, an aging temperature to be applied to the query is determined. The determined aging temperature is received at the application. The aging temperature is automatically set in the session before executing the query in the in-memory database. Based on the determined aging temperature, a partition is loaded from a secondary memory to a main memory. With the aging temperature as reference, the query is executed to fetch a result from the in-memory database.

Abstract: Approaches for performing memory management by a hypervisor. A host operating system and a hypervisor are executed on a device. The host operating system is not configured to access physical memory addressed above four gigabytes. The hypervisor manages memory for a device, including memory addressed above four gigabytes. When the hypervisor instantiates a virtual machine, the hypervisor may allocate memory pages for the newly instantiated virtual machine by preferentially using any unassigned memory addressed above four gigabytes before using memory allocated from the host (and hence addressed below four gigabytes).

Abstract: The present disclosure provides a method and electronic device for processing information. The method is applied in a solid state storage apparatus which is connected to an electronic device. The solid state storage apparatus supports N logical-address-to-physical-address mapping tables different from each other simultaneously, wherein N is an integer greater than or equal to 1. The method comprises: receiving identity information for a user from the electronic device; determining a first logical-address-to-physical-address mapping table corresponding to the user based on the identity information; and assigning the first logical-address-to-physical-address mapping table to the user.

Abstract: Systems and methods are disclosed for ensuring a target lifetime of a memory device coupled to an SoC of a computing device, the SoC including a central processing unit (CPU) executing an operating system (O/S). A DRAM is coupled to the SoC, and the memory device is configured to receive page swaps from the DRAM. A swap lifetime controller (SLC) in communication with the O/S is configured to determine a number of page swaps for the memory device during a time interval. A learning prediction system (LPS) in communication with the SLC is configured to determine a target number of page swaps (target_swap) to the memory device and a remaining life of the memory device (remaining_life_of_device). The SLC determines the number of page swaps based on the target_swap and remaining_life_of_device.

Abstract: Methods, apparatus and computer program products implement embodiments of the present invention that include storing one or more data volumes to a small computer system interface storage device, and receiving a request to map a given data volume to a host computer. One or more attributes of the given data volume are identified, and using the identified one or more attributes, a unique logical unit number (LUN) for the given data volume is generated. The given data volume is mapped to the host computer via the unique LUN. In some embodiments, the generated LUN includes one of the one or more attributes. In additional embodiments, the generated LUN includes a result of a hash function using the one or more attributes. In storage virtualization environments, the data volume may include secondary logical units, and mapping the given data volume to the host may include binding the SLU to the host.