Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

Abstract: A data storage system that provides improved reliability and performance comprises a first memory device including a plurality of first storage components and a first memory controller, the first memory controller controls operation of the first storage components, a second memory device including a plurality of second storage components and a second memory controller, the second memory controller controls operation of the second storage components, a grading device determining grades for each of the first storage components and the second storage components, and a system controller that the location of data based on the grades of the first storage components and the second storage components.

Abstract: A data storage device includes a nonvolatile memory apparatus suitable for accessing a target region corresponding to an access command, and a processor suitable for calculating a first hash value corresponding to the target region based on a first hash function, and updating an access count that is indexed by the first hash value.

Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

Abstract: A software assist module of a system memory coupled to a host processor provides the ability to offload software operations from the host processor. The software assist module includes a first memory accessed by the host processor via a first chip select signal. The software assist module also includes a software assist controller accessed by the host processor via a second chip select signal. The software assist controller is configured to intercept data related to a software function offloaded from the host processor, where the data is intercepted from a first chip select signal used to access the first memory. The software assist controller utilizes the intercepted data to perform the offloaded function. Based on configuration instructions provided by the host processor via the second chip select signal, the software assist module performs the offloaded function incrementally as function data is intercepted or as a single operation after all data for a function has been intercepted.

Abstract: Providing global values may include configuring a global memory to include a global counter and configuring processing cores to have private caches each including two sets of buffers, an update toggle and a read toggle. A processing core having a first private cache may perform processing to read a current value for the global counter including determining the current value of the global counter as a mathematical sum of a local counter value and a local delta value from one of the two sets of buffers of the first private cache identified by the read toggle. The processing core may perform processing to modify the global counter by a first amount by updating the local delta value from a specified one of the two set of buffers of the first private cache identified by the update toggle.

Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

Abstract: A method for performing access management of a memory device and associated apparatus (e.g. the memory device and controller thereof such as a memory controller within the memory device, an associated host device and an associated electronic device) are provided. The method may include: when the host device sends a host command to the memory device, utilizing the memory controller to estimate a completion time of the host command, to generate completion time information corresponding to the completion time; and utilizing the memory controller to send the completion time information to the host device, to allow the host device to perform polling after the completion time to obtain execution result of the host command.

Abstract: Described herein are systems, methods, and software to improve incident response in an information technology (IT) environment. In one example, an incident service executes a course of action with one or more actions to respond to an incident in the IT environment. During execution, the incident service identifies a request to obtain data from an external service outside of the IT environment and determines whether the data is cached in a data store for the IT environment. If cached, the incident service obtains the data for the action from the data store. In contrast, if the data is not cached, the incident service obtains the data for the action from the external service.

Abstract: An example method includes maintaining a first data structure comprising logical address to physical address mappings for managed units corresponding to a memory, and maintaining a second data structure whose entries correspond to respective physical managed unit addresses. Each entry of the second data structure comprises an activity counter field corresponding to the respective physical managed unit address and a number of additional fields indicating whether the respective physical managed unit address is in one or more of a number of additional data structures. The one or more additional data structures are accessed in association with performing at least one of a wear leveling operation on the respective physical managed unit address, and a neighbor disturb mitigation operation on physical managed unit addresses corresponding to neighbors of the respective physical managed unit address.

Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

Abstract: A method for writing multiple copies into a storage device includes receiving a first write data request that includes an identity (ID) of a first logical storage unit, target data, and a logical block address (LBA) of the first logical storage unit, determining that data stored in storage space corresponding to the LBA of the first logical storage unit is not accessed by another data access request, writing the target data into the storage space corresponding to the LBA of the first logical storage unit, generating a second write data request that includes an ID of a second logical storage unit, the target data, and an LBA of the second logical storage unit, and writing the target data into storage space corresponding to the LBA of the second logical storage unit.

Abstract: Memory is dynamically shared or allocated in an embedded computer system. The types of memory that are part of the system are first determined. Thereafter, the amount of memory available for use is determined. The type of memory required by a program or application is determined as is the amount of space that is required. If the amount of memory space that can be allocated to the program in a first type of requested memory is greater than or at least equal to the amount of memory space required by the computer program, the program is then loaded into the available memory. If the requested type of memory is not available or there is not enough of the requested memory available, other types of memory devices are considered and used, if sufficient space in one or more of them exists.

Abstract: An apparatus for cache coherency between a device and a processor includes a buffer module that buffers data in a non-cache coherent space of an electronic device communicatively coupled to a processor. The apparatus includes an update module that updates at least one identifier with respect to the buffered data. The at least one identifier is stored in a cache coherent space of the electronic device. The apparatus includes a coherence notification module that notifies the processor of a cache incoherence. The cache incoherence indicates that the cache coherent space of the electronic device that includes the updated at least one identifier differs from a cache coherent space of the processor that includes a copy of the at least one identifier prior to the update.

Abstract: Aspects disclosed herein include memory controllers employing memory capacity compression, and related processor-based systems and methods. In certain aspects, compressed memory controllers are employed that can provide memory capacity compression. In some aspects, a line-based memory capacity compression scheme can be employed where additional translation of a physical address (PA) to a physical buffer address is performed to allow compressed data in a system memory at the physical buffer address for efficient compressed data storage. A translation lookaside buffer (TLB) may also be employed to store TLB entries comprising PA tags corresponding to a physical buffer address in the system memory to more efficiently perform the translation of the PA to the physical buffer address in the system memory. In certain aspects, a line-based memory capacity compression scheme, a page-based memory capacity compression scheme, or a hybrid line-page-based memory capacity compression scheme can be employed.

Abstract: Apparatus and method for data security using adaptive selection of intrusion traps in relation to workload. In some embodiments, a data storage device has a non-volatile memory (NVM). A device controller circuit services data transfer commands received from a host device to transfer data between the host device and the NVM. A security controller circuit monitors the received data transfer commands and enacts a change in security policy to implement one or more intrusion traps associated with the NVM in response to the received data transfer commands. The intrusion traps constitute memory locations that are configured to normally store user data, but are not normally accessed during the servicing of the currently received data transfer commands.

Abstract: A data storage device may be configured to direct access to at least a portion of a host memory of a host device. For example, the data storage device may store data at the host memory, such as data predicted to be subject to a read request from the host device. When the data storage device receives a read request from the host device to read the data, the data storage device may send an indication to the host device to enable the host device to read the data directly from the host memory.

Abstract: Example embodiments of the present invention relate and a method and an apparatus for managing a short hash handle. The method including receiving an I/O including a first identifier for a data block and examining the first identifier in comparison with a second identifier. The data block identified in the I/O then may be managed according to the first identifier and the second identifier.

Abstract: A storage cluster includes a plurality of storage nodes. Each of the plurality of storage nodes includes nonvolatile solid-state memory and each of the plurality of storage nodes is configured to cooperate with others of the plurality of storage nodes having differing storage capacities in applying erasure coding. The plurality of storage nodes are configured to distribute the user data and metadata throughout the plurality of storage nodes.

Abstract: A computing system comprises one or more cores. Each core comprises a processor and switch with each processor coupled to a communication network among the cores. Also disclosed are techniques for implementing an adaptive last level allocation policy in a last level cache in a multicore system receiving one or more new blocks for allocating for storage in the cache, accessing a selected profile from plural profiles that define allocation actions, according to a least recently used type of allocation and based on a cache action, a state bit, and traffic pattern type for the new blocks of data and handling the new block according to the selected profile for a selected least recently used (LRU) position in the cache.