Patents Examined by Stephen C. Elmore
  • Patent number: 7562203
    Abstract: A method in a storage system reads blocks having both physical addresses and logical addresses in the storage system from a first set of locations in non-volatile storage to a cache memory and determines the level of data fragmentation in the non-volatile storage. If the level of data fragmentation exceeds a threshold level, the cache memory is marked and the blocks are written to physically sequential locations with new physical addresses in the non-volatile storage at a data consistency point without changing the logical addresses of the blocks.
    Type: Grant
    Filed: September 27, 2006
    Date of Patent: July 14, 2009
    Assignee: Network Appliance, Inc.
    Inventors: John A. Scott, Eric C. Hamilton
  • Patent number: 7562195
    Abstract: A system calculates the optimal allocation of two or more resources provided by a resource provider to a task within a computer system from a plurality of possible allocations. In doing so, the system calculates the total volume of an N-dimensional cube, where N is the number of resources provided by the resource provider, representing the respective amounts of resources available to be allocated. The system also calculates the average volume of the N-1 dimensional shapes forming the sides of the N-dimensional cube. The system then calculates, at least partly from the ratio of the total volume to the average volume, the balance resulting from the allocation of resources represented by the N-dimensional cube. The system then calculates the imbalance resulting from the allocation of resources at least partly from the balance and determines the smallest imbalance as the optimal allocation of resources.
    Type: Grant
    Filed: November 29, 2006
    Date of Patent: July 14, 2009
    Assignee: Teradata US, Inc.
    Inventors: Peter Frazier, Paul Andersen, Gary Boggs, Criselda Carrillo, Donn Holtzman, John Mark Morris, P. Keith Muller, Ronald Yellin
  • Patent number: 7555607
    Abstract: In a method of and system for program thread synchronization, an instruction cache line is determined each of a plurality of program threads to be synchronized. For each processor executing one or more of the threads to be synchronized, execution of the thread is halted at a barrier by rendering the determined instruction cache line unavailable. Execution of the threads resumes by rendering the determined instruction cache lines available.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: June 30, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jean-Francois C. P. Collard, Norman Paul Jouppi, Michael S. Schlansker
  • Patent number: 7555597
    Abstract: Methods and apparatus to perform direct cache access in multiple core processors are described. In an embodiment, data corresponding to a direct cache access request is stored in a storage unit and a corresponding read request is generated. Other embodiments are also described.
    Type: Grant
    Filed: September 8, 2006
    Date of Patent: June 30, 2009
    Assignee: Intel Corporation
    Inventors: Durgesh Srivastava, Jeffrey D. Gilbert
  • Patent number: 7552281
    Abstract: An apparatus processes data using an external memory. In the apparatus, an external memory power supply provides power to the external memory. An external memory insertion detector detects insertion/removal of the external memory, and continues to detect an inserted state of the external memory when the power provided from the external memory power supply is cut off in the inserted state of the external memory. A first controller provides power to the external memory by controlling the external memory power supply, when the external memory is in use, and cuts off the power provided to the external memory by controlling the external memory power supply, when the external memory is not in use, generates a data list by detecting data from the external memory, and processes normal data in the data stored in the external memory. A second controller processes video data in the data stored in the external memory.
    Type: Grant
    Filed: January 27, 2006
    Date of Patent: June 23, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sung-Hwa Gong
  • Patent number: 7546410
    Abstract: A self timed memory chip having an apportionable data bus. Access timing to an array on the memory chip is dynamically determined by circuitry on the memory chip. A ring oscillator on the memory chip has a frequency that is indicative of how fast an array on the memory chip can be accessed. The ring oscillator includes a bit line that is periodically charged and a memory element that subsequently discharges the bit line. The memory chip has a data bus interface having a number of bits. The data bus interface has a first number of bits apportioned to write data and a second number of bits apportioned to read data. The first number of bits and the second number of bits is programmable.
    Type: Grant
    Filed: July 26, 2006
    Date of Patent: June 9, 2009
    Assignee: International Business Machines Corporation
    Inventors: Gerald Keith Bartley, Darryl John Becker, John Michael Borkenhagen, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson
  • Patent number: 7543128
    Abstract: In one embodiment, at least one characteristic of an ecosystem is monitored. The ecosystem includes i) a plurality of compute resources, and ii) a number of storage applications, wherein the number of storage applications are configured to use a plurality of storage access protocols. Which of the storage access protocols are implemented by which of the compute resources are tracked; and in response to the monitored characteristic(s) of the ecosystem being found unacceptable, an attempt is made to improve the monitored characteristic(s) by repurposing one or more of the compute resources to implement, or not implement, one of the storage access protocols.
    Type: Grant
    Filed: July 25, 2006
    Date of Patent: June 2, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Harold Woods, Douglas L. Voigt
  • Patent number: 7536508
    Abstract: An active-active RAID system includes first and second active-active RAID controllers which efficiently share access to SATA drives. SAS expanders connect the RAID controllers to the drives. The controllers establish an affiliation within the SAS expanders with respectively-owned first and second subsets of the SATA drives. The controllers directly transmit to the SAS expanders commands destined for affiliated drives, but forward to the other RAID controller, via an inter-controller communications link, commands destined for unaffiliated drives for transmission by the other RAID controller. The controllers handle drive ownership changes by clearing previously-established affiliations, updating ownership data stored on the drives, including forwarding the update commands as necessary, and re-establishing affiliations based on the new ownership.
    Type: Grant
    Filed: November 7, 2006
    Date of Patent: May 19, 2009
    Assignee: Dot Hill Systems Corporation
    Inventor: Ian Robert Davies
  • Patent number: 7536525
    Abstract: A system and method for hot cloning in a distributed network is disclosed. In one embodiment, a method for cloning a virtual machine from a source system to a target system includes freezing writes to a storage file having storage blocks such that subsequent writes create new storage blocks for the original virtual machine. The method further including freezing writes to a memory content such that subsequent writes store in buffers. The method further including copying the memory content onto the target system wherein the copied memory content creates a clone. The method further including unfreezing the memory content by merging the writes stored in the buffers and unfreezing the writes to the storage file such that subsequent writes take place normally. The method further including configuring the clone based on the target system. The method further including creating a new storage block for any writes to the storage file whereby the new storage block is not shared.
    Type: Grant
    Filed: November 9, 2004
    Date of Patent: May 19, 2009
    Assignee: Dell Products L.P.
    Inventors: Balasubramanian Chandrasekaran, Timothy E. Abels
  • Patent number: 7536519
    Abstract: A memory controller determines a load level based on the number of connected memory devices informed by a switch or the like. If it is determined that the load level is high, the memory controller increases the number of cycles for issuing command/address signals, and if it is determined that the load level is low, the memory controller reduces the number of issuing cycles.
    Type: Grant
    Filed: June 2, 2005
    Date of Patent: May 19, 2009
    Assignee: Canon Kabushiki Kaisha
    Inventor: Kohei Murayama
  • Patent number: 7533239
    Abstract: A self-tuning, low overhead, simple to implement, locally adaptive, novel cache management policy that dynamically and adaptively partitions the cache space amongst sequential and random streams so as to reduce read misses.
    Type: Grant
    Filed: February 19, 2008
    Date of Patent: May 12, 2009
    Assignee: International Business Machines Corporation
    Inventors: Binny Sher Gill, Dharmendra Shantilal Modha
  • Patent number: 7529900
    Abstract: There is provided a computer system which can implement ease of transition to a standby state caused by power-off of a volume and ease of recovery from a standby state while maintaining access performance. A computer system including a storage system (200) having one or more disk units (220) and a disk controller unit (210) which controls reading and writing of data stored on volumes formed by the disk units and a host computer (100) which transmits a data read/write request to the storage system (200), wherein the host computer (100) gives an instruction to perform volume assignment for each of groups each having duplicated sets obtained by multiply duplicating a set composed of one or more volumes on which data is to be stored, and the storage system (200) assigns a first volume of a first duplicated set in the group to one of the disk units (220) which has an attribute different from an attribute of a volume constituting another duplicated set.
    Type: Grant
    Filed: June 12, 2006
    Date of Patent: May 5, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Yuri Hiraiwa, Masaaki Hosouchi, Katsuhisa Miyata, Nobuhiro Maki
  • Patent number: 7526598
    Abstract: A driver for a data storage device includes an access command and a verification command. The access command initiates an access (write, erase or read) of the data storage device while allowing a calling application to continue running without having to wait for the completion of the access. The verification command queries a preceding access. If the query indicates failure of the preceding access, the verification command repeats the preceding access until the preceding access succeeds. The verification command is called by the access command before the access command initiates a new access. The verification command also is called by an application following a sequence of related access command calls. A write access command saves the data to be written in a memory separate from the data storage device, in case the verification command needs that data to repeat a failed write.
    Type: Grant
    Filed: March 3, 2003
    Date of Patent: April 28, 2009
    Assignee: SanDisk IL, Ltd.
    Inventors: Ori Stern, Menahem Lasser
  • Patent number: 7526606
    Abstract: Various apparatus and methods for controlling data for a redundant array of inexpensive/independent disks (RAID) are presented. For example, in one illustrative embodiment, a controlling apparatus can include a translation device capable of reading data from a plurality of N disks, wherein the data of the N disks has a format consisting of a sequence of block stripes with each block containing one or more sector stripes, and wherein each sector stripe is formatted such that N?1 of the sectors contain contiguous target data and the remaining sector contains parity data for the other N?1 target data sectors.
    Type: Grant
    Filed: September 8, 2006
    Date of Patent: April 28, 2009
    Assignee: Agere Systems, Inc.
    Inventors: Richard J. Byrne, Silvester Tjandra, Eu Gene Goh
  • Patent number: 7526621
    Abstract: Provided are a method, system, and program for receiving a request to remove a record. A determination is made as to whether a state associated with the record includes at least one hold state and whether the state associated with the record includes at least a retention period that has not expired. The request to remove the record is denied in response to determining that the state associated with the record includes at least one of at least one hold state and one retention period that has not expired.
    Type: Grant
    Filed: August 18, 2006
    Date of Patent: April 28, 2009
    Assignee: International Business Machines Corporation
    Inventors: Alan L. Stuart, Toby Lyn Marek, Avishai Haim Hochberg, David Maxwell Cannon, Howard Newton Martin
  • Patent number: 7523261
    Abstract: A method for changing a succession of instruction words including providing a set of machine words, each machine word being associated with an address from a set of addresses, providing a succession of instruction words having address information, the succession of instruction words prescribing a sequence of machine words which are intended to be processed by an arithmetic and logic unit which is coupled to a buffer store, altering the association between at least a portion of the set of machine words and at least a portion of the set of addresses, changing the address information in the succession of instruction words based on the alteration of the association, storing the changed succession of instruction words in a memory, and storing the set of machine words in the memory, so that it is possible to access the machine words using the associated addresses.
    Type: Grant
    Filed: November 6, 2006
    Date of Patent: April 21, 2009
    Assignee: Infineon Technologies AG
    Inventors: Josef Haid, Michael Smola, Dietmar Scheiblhofer
  • Patent number: 7523266
    Abstract: One embodiment of the present invention provides a system that enforces memory reference ordering requirements, such as Total Store Ordering (TSO), at a Level 1 (L1) cache in a multiprocessor. During operation, while executing instructions in a speculative-execution mode, the system receives an invalidation signal for a cache line at the L1 cache wherein the invalidation signal is received from a cache-coherence system within the multiprocessor. In response to the invalidation signal, if the cache line exists in the L1 cache, the system examines a load-mark in the cache line, wherein the load-mark being set indicates that the cache line has been loaded from during speculative execution. If the load-mark is set, the system fails the speculative-execution mode and resumes a normal-execution mode from a checkpoint.
    Type: Grant
    Filed: November 3, 2006
    Date of Patent: April 21, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: Shailender Chaudhry, Marc Tremblay
  • Patent number: 7523269
    Abstract: Systems and methods of sharing files and data in memory between the two operating systems running on a computing device. A main operating system (OS) may execute on the computing device an provide numerous system features and functionality. To conserver power, the main OS may unload, or the computer may be reset, suspended or be shutdown. Prior to doing so, the main OS writes data to a known memory location that allows access by a secondary OS when the main OS is not present. The secondary OS provides a limited set of functionalities, while being able to use and interact with the data stored in the known memory location. Information about the data and permissions are stored in mailbox that is accessible to both operating system such that changes made when the secondary operating system is active are synchronized with the main operating system.
    Type: Grant
    Filed: July 22, 2005
    Date of Patent: April 21, 2009
    Assignee: Microsoft Corporation
    Inventors: Ruston Panabaker, Pasquale DeMaio, William Jefferson Westerinen
  • Patent number: 7519773
    Abstract: A cache on-demand module employing a cache performance module for managing size adjustments to a cache size of a cache memory in view of supporting an optimal performance of a storage subsystem employing the cache memory by determining an optimal cache size of the cache memory for supporting the optimal performance of the storage subsystem, and reporting any size adjustment to the cache size of the cache memory based on the determined optimal cache size of the cache memory. The cache on-demand module further employs a cache accounting module for managing a client expense account associated with the cache memory by determining whether a client charge or a client rebate is warranted as a function of any size adjustment to the cache size of the cache memory by the cache performance module.
    Type: Grant
    Filed: November 21, 2007
    Date of Patent: April 14, 2009
    Assignee: International Business Machines Corporation
    Inventor: Andrew B. McNeill, Jr.
  • Patent number: 7519767
    Abstract: A system, method and a computer program product for emulating a tape-based storage system to provide data storage. The system includes a data storage medium storing a data set which represents the data layout of the emulated tape-based medium, and an interface for providing access to a non-tape-based data storage medium, using tape-based media commands and using the data set. The fist data set includes filemark location data and block number data for mapping between filemark locations and block numbers of the emulated tape-based storage medium and the non-tape-based data storage medium.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: April 14, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Alastair Michael Slater