Patents Examined by Stephen C. Elmore
  • Patent number: 7475189
    Abstract: Systems and methodologies that enable restoration of data by software solutions and in the absence of a hardware RAID adapter, via encapsulation of a RAID (Redundant Array of Independent/or Inexpensive Disks) format, by employing a Globally Unique Identifier (GUID) Partition Table (GPT). Third party vendors can employ proprietary data recovery software to access the raw data in case of malfunction of an associated RAID adapter. Moreover, the subject invention can facilitate inter-operability among a plurality of RAID adapters, to move array sets from one controller type to another.
    Type: Grant
    Filed: March 4, 2005
    Date of Patent: January 6, 2009
    Assignee: Microsoft Corporation
    Inventor: Henry P Gabryjelski
  • Patent number: 7475200
    Abstract: A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier or sequence number. The mechanism is placed between a processing element and a memory system such that write data is buffered and information based upon reads and writes is recorded. Information is maintained, including a write dependency list, allowing for the detection of memory conflicts. When a memory conflict is detected, a restart signal is generated and the entries for the associated sequence number are flushed. Further, the write dependency list is consulted to determine if other packets have been potentially corrupted and also need to be flushed. Upon detection of dependent packets that have potentially been corrupted, further packet restart signals are generated and sent to the packet processing engine.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: January 6, 2009
    Assignee: Teplin Application Limited Liability Company
    Inventor: Stephen Waller Melvin
  • Patent number: 7475201
    Abstract: A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier or sequence number. The mechanism is placed between a processing element and a memory system such that write data is buffered and information based upon reads and writes is recorded. Upon receiving a memory write, conflict detection logic determines if a conflict has occurred and if packet processing for a packet needs to be restarted. When such a conflict occurs, restart logic conditionally delays the restart to the packet processing engine. This can be accomplished using a stall signal or by delaying the return of the first memory read after the restart. Such a conditional delayed restart mechanism can optimize processing based on the likelihood of multiple conflicts or a single conflict.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: January 6, 2009
    Assignee: Teplin Application Limited Liability Co.
    Inventor: Stephen Waller Melvin
  • Patent number: 7475210
    Abstract: An address processing section allocates addresses of desired data in a main memory, input from a control block, to any of three hit determination sections based on the type of the data. If the hit determination sections determine that the data stored in the allocated addresses does not exist in the corresponding cache memories, request issuing sections issue transfer requests for the data from the main memory to the cache memories, to a request arbitration section. The request arbitration section transmits the transfer requests to the main memory with priority given to data of greater sizes to transfer. The main memory transfers data to the cache memories in accordance with the transfer requests. A data synchronization section reads a plurality of read units of data from a plurality of cache memories, and generates a data stream for output by a stream sending section.
    Type: Grant
    Filed: December 19, 2005
    Date of Patent: January 6, 2009
    Assignee: Sony Computer Entertainment Inc.
    Inventor: Hideshi Yamada
  • Patent number: 7472239
    Abstract: Provided are a storage system and data management method capable of improving the usage efficiency of a storage extent. With this storage system, a first storage apparatus dynamically allocates a storage extent to the first volume and sends data written by the host system in the first volume to the second storage apparatus; a second storage apparatus writes the data sent from the first storage apparatus in a corresponding position in the second volume pair-configured with the first volume and stores as management information the position to which the data from the first storage apparatus in the second volume was written; and the second storage apparatus, during the restoration processing of the first volume, refers to the management information and sends to the first storage apparatus the data in a position to which the data from the first storage apparatus in the second volume was written.
    Type: Grant
    Filed: May 11, 2006
    Date of Patent: December 30, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Takeshi Horiuchi, Ryusuke Ito
  • Patent number: 7467259
    Abstract: Systems and methods are provided for generating a snapshot that records desired data, while allowing a client server to continue sending data to the storage system. In an example of an embodiment of the invention, a method is provided for recording data generated by a client server and transmitted to a storage system. The method comprises storing data, received from the client server, in the storage system, and receiving a command from the client server to perform a snapshot of the data. The method further comprises generating a snapshot of the data stored in the storage system in response to the command.
    Type: Grant
    Filed: January 11, 2007
    Date of Patent: December 16, 2008
    Assignee: Falcon Stor, Inc.
    Inventor: Wai Lam
  • Patent number: 7464247
    Abstract: An improved system and method for importing update data in a distributed column chunk data store is provided. A distributed column chunk data store may be provided by multiple storage servers operably coupled to a network. A storage server provided may include a database engine for partitioning a data table into the column chunks for distributing across multiple storage servers, a storage shared memory for storing the column chunks during processing of semantic operations performed on the column chunks, and a storage services manager for striping column chunks of a partitioned data table across multiple storage servers. Any data table may be flexibly partitioned into column chunks using one or more columns with various partitioning methods. Update data may then be incrementally imported as separate column chunks that may later be merged with the column chunks of the partitioned data table.
    Type: Grant
    Filed: December 19, 2005
    Date of Patent: December 9, 2008
    Assignee: Yahoo! Inc.
    Inventor: Radha Krishna Uppala
  • Patent number: 7464230
    Abstract: A method for memory controlling is disclosed. It includes an embedded address generator and a controlling scheme of burst terminates burst, which could erase the latency caused by bus interface during the access of non-continuous addresses. Moreover, it includes a controlling scheme of anticipative row activating, which could reduce the latency across different rows of memory by data access. The method could improve the access efficiency and power consumption of memory.
    Type: Grant
    Filed: September 8, 2006
    Date of Patent: December 9, 2008
    Inventors: Jiun-In Guo, Chih-Ta Chien, Chia-Jui Huang
  • Patent number: 7461226
    Abstract: Two storage areas are created in a first storage subsystem, a synchronous remote copy is performed from a first storage area included in the first storage subsystem to a storage area included in a second storage subsystem, and an asynchronous remote copy is performed from a second storage area included in the first storage subsystem to a storage area included in a third storage subsystem. Besides, a computer accessing the first storage subsystem performs mirroring to both the storage areas included in the first storage subsystem.
    Type: Grant
    Filed: April 26, 2007
    Date of Patent: December 2, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Takashige Iwamura, Takashi Oeda, Takao Satoo
  • Patent number: 7461197
    Abstract: A disk formatter includes an address module for creating disk block address data corresponding to a disk sector of a disk drive. A sector write module initiates a physical mode write operation to the disk sector that incorporates the corresponding disk block address data.
    Type: Grant
    Filed: December 19, 2005
    Date of Patent: December 2, 2008
    Assignee: Broadcom Corporation
    Inventors: Bob R. Southerland, John Mead, Kevin W. McGinnis
  • Patent number: 7451271
    Abstract: A virtually indexed, physically-tagged cache is combined with one or more virtually-tagged fill-buffers.
    Type: Grant
    Filed: April 5, 2004
    Date of Patent: November 11, 2008
    Assignee: Marvell International Ltd.
    Inventor: Dennis M. O'Connor
  • Patent number: 7444459
    Abstract: Methods and systems for generating storage related load factor information for load balancing of multiple virtual machines operable in a cluster of multiple physical processors (such as a blade center). Load factor information is generated within a storage system relating to operation of the storage system as a whole and relating to each of multiple storage controllers in the storage system. The information so generated in the storage system is communicated to a load balancing element associated with the multiple virtual machines. The load balancing element then utilizes the storage related load factor information, optionally in combination with other load factor information, to distribute or redistribute the operation of the multiple virtual machines over the plurality of physical processors.
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: October 28, 2008
    Assignee: LSI Logic Corporation
    Inventor: Stephen B. Johnson
  • Patent number: 7444481
    Abstract: A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier. The mechanism is placed between a processing element and a memory system such that write data is buffered and information based upon both reads and writes is recorded. Information is maintained allowing the detection of memory conflicts. When a potential memory conflict is detected, the values associated with the potentially conflicting memory operations are compared. In cases where the values match, no conflict is signaled. Such a value checking mechanism reduces the number of restarts needed in certain cases.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: October 28, 2008
    Assignee: Teplin Application Limited Liability Company
    Inventor: Stephen Waller Melvin
  • Patent number: 7444482
    Abstract: A method, apparatus, and computer program product for storage pools with write atomicity. An abstraction manager enforces write atomicity and disallows options which are inconsistent with write atomicity. The abstraction manager constructs through a physical device interface a logical continuous view of a storage pool in a manner consistent with write atomicity. Applications collect information specific to write atomicity from the abstraction manager through an application interface.
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: October 28, 2008
    Assignee: International Business Machines Corporation
    Inventors: Matthew Albert Huras, Thomas Stanley Mathews, Lance Warren Russell
  • Patent number: 7441088
    Abstract: A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier. Upon receiving a memory read, conflict prediction logic determines if a future conflict with a memory write is likely, and if so the processing of the memory read is delayed. After the write to which the read depends is received, the delayed memory read is allowed to complete. Such a delayed read mechanism can reduce or eliminate work discarded due to memory conflicts detected after the fact, while preserving the sequential semantics of the packet processor. The conflict prediction logic can be used in conjunction with conflict detection in which write data is buffered and information associated with both reads and writes is recorded.
    Type: Grant
    Filed: September 11, 2006
    Date of Patent: October 21, 2008
    Assignee: Teplin Application Limited Liability Company
    Inventor: Stephen Waller Melvin
  • Patent number: 7437503
    Abstract: Embodiments of the present invention provide for implementation of data transfers in an efficient manner. The 48-bit LBA mechanism requires two sets of I/O writes to IDE registers on primary channel or secondary channel. The two sets of I/O writes to the primary or secondary channel registers are performed by setting a status register to a first or second state appropriately depending on the data. Embodiments of the present invention provide a single set of writes to I/O registers when the size of the data transfer is equal to or below a threshold value.
    Type: Grant
    Filed: April 25, 2005
    Date of Patent: October 14, 2008
    Assignee: Intel Corporation
    Inventors: Rajeev K Nalawadi, Steve P Mooney
  • Patent number: 7437504
    Abstract: Provides methods, systems and devices for reading a storage medium. A method for reading a storage medium according to the invention includes the following steps: First, it is determined if an access sequence requested by an application to data stored on the disk drive is a part of a known access sequence. Then, if the requested access sequence is part of a known access sequence, the data are read from a data arrangement stored on the medium in addition to an original data arrangement which additional data arrangement differs in its arrangement of data from the arrangement of data in the original data arrangement.
    Type: Grant
    Filed: July 21, 2005
    Date of Patent: October 14, 2008
    Assignee: International Business Machines Corporation
    Inventor: Marcel Waldvogel
  • Patent number: 7428616
    Abstract: An information processing apparatus has a CPU, a memory, a cache memory and a cache controller. When an acquisition of an area of a prescribed size is requested in the memory, a size equivalent to at least two lines serving as a cache unit is added to the prescribed size requested and this area is reserved in the memory. The area reserved is allocated to an uncacheable memory area of this memory.
    Type: Grant
    Filed: January 28, 2005
    Date of Patent: September 23, 2008
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takeshi Ogawa, Takeo Sakimura
  • Patent number: 7426626
    Abstract: A processor includes a hierarchical Translation Lookaside Buffer (TLB) comprising a Level-1 TLB and a small, high-speed Level-0 TLB. Entries in the L0 TLB replicate entries in the L1 TLB. The processor first accesses the L0 TLB in an address translation, and access the L1 TLB if a virtual address misses in the L0 TLB. When the virtual address hits in the L1 TLB, the virtual address, physical address, and page attributes are written to the L0 TLB, replacing an existing entry if the L0 TLB is full. The entry may be locked against replacement in the L0 TLB in response to an L0 Lock (L0L) indicator in the L1 TLB entry. Similarly, in a hardware-managed L1 TLB, entries may be locked against replacement in response to an L1 Lock (L1L) indicator in the corresponding page table entry.
    Type: Grant
    Filed: August 23, 2005
    Date of Patent: September 16, 2008
    Assignee: QUALCOMM Incorporated
    Inventors: Victor Roberts Augsburg, James Norris Dieffenderfer, Jeffrey Todd Bridges, Thomas Andrew Sartorius
  • Patent number: 7418546
    Abstract: Provided is a computer system including a storage subsystem, a host computer, and a management computer for managing the storage subsystem and the host computer. The storage subsystem manages a storage extent by a group unit and creates storage extent configuration information. The management computer stores group management information, obtains the storage extent configuration information, calculates an assigned capacity for each group based on the obtained storage extent configuration information, forecasts a capacity to be assigned in the future for each group based on the calculated assigned capacity, calculates a protection term expired capacity for each group based on the group management information and the storage extent configuration information, and outputs the assigned capacity, the capacity to be assigned in the future, and the protection term expired capacity. Thus, the storage extent of the storage subsystem can easily be managed.
    Type: Grant
    Filed: October 26, 2005
    Date of Patent: August 26, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Yuichi Taguchi, Fumi Miyazaki, Masayuki Yamamoto