Abstract: One embodiment of the present invention provides a system that enforces memory-reference ordering requirements at an L2 cache. During operation, the system receives a load at the L2 cache, wherein the load previously caused a miss at an L1cache. Upon receiving the load, the system performs a lookup for the load in reflections of store buffers associated with other L1 caches. These reflections are located at the L2 cache, and each reflection contains addresses for stores in a corresponding store buffer associated with an L1 cache, and possibly contains data that was overwritten by the stores. If the lookup generates a hit, which indicates that the load may potentially interfere with a store, the system causes the load to wait to execute until the store commits.

Abstract: Circuits, methods, and apparatus for efficiently storing page characteristics. Page characteristics for memory pages are stored post address translation using addresses for physical locations in memory, for example, in a bit vector. The characteristics may include access or dirty bits, as well as other types of information. These bit vectors can also be stored and accumulated to generate histogram data. Two bit vectors may be included, while a first bit vector is written to, another is used. After data has been written to the first, the bit vectors are flipped, and data is written to the second while the first is used.

Abstract: A control device for a memory is provided. The control device includes a micro-control unit (MCU), a command queue, a command sequencer, and a table. The control device is coupled to the memory and is used for controlling the memory to execute an operation. In which, the MCU outputs a control signal according to the operation. The command sequencer sequentially stores command sets required by the execution of the operation according to the control signal, and each command set includes plural commands. The command queue sequentially stores command set contents according to the order of the corresponding command sets. The table stores a target address of the memory required by the execution of the operation.

Abstract: Disclosed is a memory controller which is disposed between a CPU and a memory, receives from the CPU a control signal (TRANS) indicating whether a type of a bus cycle is a sequential cycle in which an address continuous with an address of an immediately preceding bus cycle is output to the memory as an address of a current bus cycle or a nonsequential cycle in which an address unrestricted by the address of the immediately preceding bus cycle is output to the memory as an address of a current bus cycle. The memory controller outputs a control signal (RDY) for notifying completion of the bus cycle to the CPU. In this memory controller, an address assuming the sequential cycle is generated in advance from the current address before completion of the bus cycle. Then, the address assuming the sequential cycle is supplied to the memory in a next cycle. Read data from the memory corresponding to the address assuming the sequential cycle is then output to the CPU.

Abstract: The claimed subject matter provides systems and/or methods that facilitate sharing of a memory, having a single channel of access, between two or more processors. A host processor can be operatively connected to a co-processor and the memory in series. The host processor can execute in place to enable it to execute code directly from the memory, and can arbitrate access to the memory bus and thus the memory, so that the host processor can perform all memory fetches to the memory without interruption by the co-processor. The co-processor can be implemented as a finite state machine, and only accesses the memory during read or write cycles issued by the host processor. Various types of co-processors can be employed to perform various functions, such as cryptography and digital signal processing, for example. The memory can be volatile or non-volatile memory.

Abstract: Provided is a technology in which: a request-source storage device provides a request-source server device with a storage area of a disk drive as at least one logical volume; the request-source server device determines, upon receiving a request to back up data stored in a first logical volume, whether a second logical volume which constitutes a copy pair with the first logical volume is present in the request-source storage device; the request-source server device requests, upon determining that the second logical volume is not present, the request-source storage device to produce the second logical volume; and the request-source server device transmits a request to execute a process to back up data stored in the existing or produced second logical volume to the backup storage device to the request-destination server device. Accordingly, data to be stored in a NAS not locally coupled to a backup device is appropriately backed up.

Abstract: A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier or sequence number. The mechanism is placed between a processing engine and a memory system such that write data is buffered and information based upon reads and writes is recorded. Memory read data is returned speculatively since the packet processing engine is processing packets in parallel and not necessarily in sequence. Information is maintained allowing the detection of a speculative read that was incorrect (i.e. a memory conflict). When a memory conflict is detected, a restart signal is generated and the information for the associated packet identifier or sequence number is flushed.

Abstract: Methods, systems and apparatus for maintaining colors and color boundaries across multiple storage controllers by instructing a polling storage controller to poll a color control node for current color information, changing the current color to a new color, and instructing the polling storage controller to cease polling the color control node for the current color information.

Abstract: A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier or sequence number. The mechanism is placed between the packet processing engine and a memory system such that write data is buffered and information based upon both reads and writes is recorded. Information is maintained allowing the detection of memory conflicts. Both a strict and alternate packet ordering are evaluated, such that the semantic ordering of packets is delayed until necessary to ensure that a consistent order exists. Such a late order binding mechanism is used to allow packets to be defined in any order so long as they obey a consistent order, thereby reducing the number of packet restarts and increasing overall efficiency.

Abstract: A method of communicating memory mapped page priorities includes a software application storing page priority information for a memory mapped file on a computer readable medium, and an operating system reading the page priority information.

Abstract: A storage system includes operational control information stored in RAID disk drives for higher access performance over the case where control information is stored in shared memory. The operational control information includes monitor information, log information, and copy difference management information.

Abstract: A processing system coupled to an apparatus is provided. The processing system includes: a non-volatile memory (NVM) storing firmware needed by the processing system; and an NVM control interface writing and reading data stored in the NVM. The apparatus verifies a previous piece of data being already written into the NVM, and the NVM control interface writes a current piece of data into the NVM.

Abstract: A method and system is introduced for allowing removal of a removable device connected to a digital appliance in a safe manner that preserves removable device integrity. There is no requirement for taking any actions prior to removing the removable device such as to safely remove the device. The user can intuitively tell removable device is in a state that can be safely removed and remove the device. Following a state where device can be safely removed, digital appliance can make use of removable device if the removable device had not been removed from the digital appliance.

Abstract: A mechanism receives start and done commands containing packet identifiers or sequence numbers from a packet processing engine for packets for which processing is being started and for which processing has completed respectively. Upon receiving a packet start command, an entry in an active packet list is created. Upon receiving a packet done command, the active packet list is updated. The oldest done packet in the active list is retired by flushing buffered write information to a memory system. The active packet list can be used in conjunction with a system supporting speculative reads and conflict detection. In some embodiments the packet start command is inferred from a read command containing a packet identifier or sequence number.

Abstract: Methods and systems are described for performing storage operations on electronic data in a network. In response to the initiation of a storage operation and according to a first set of selection logic, a media management component is selected to manage the storage operation. In response to the initiation of a storage operation and according to a second set of selection logic, a network storage device to associate with the storage operation. The selected media management component and the selected network storage device perform the storage operation on the electronic data.

Abstract: In a system where a storage device is coupled to a computer, a storage area in the storage device is efficiently allocated to the computer. The system comprises a virtualization apparatus to be coupled to the virtualization apparatus. The virtualization apparatus, responding to a request from the computer, issues a notice to the effect that a predetermined size of virtual volume has been allocated to the computer. The virtualization apparatus, upon receiving an access request from the computer to the virtual volume, allocates storage areas existing in a plurality of storage devices to the virtual volume, converts the access request received from the computer to an access request addressed to a storage device having the storage devices allocated to the virtual volume, and transmits the converted access request to the storage device.

Abstract: A data processing system incorporating watchpoint registers is provided. The memory accesses to be detected may be unaligned memory accesses. The watchpoint may operate in a normal mode and also in a guard mode. In the guard mode of operation a watchpoint comparator generates a match signal if the upper N bits of the memory address match the upper end bits of the watchpoint address and the length of the memory access L is such that the memory access extends to include a memory address having a different upper N bits but located at a predetermined address offset P from the watchpoint address W.

Abstract: A point-in-time image of data in stored in a storage system is identified. Dependencies from the point-in-time image are detected. The dependencies are broken in an order before the point-in-time image is deleted. In one embodiment, an order in which to break the dependencies is presented to a user via one or more graphs. Based on the one or more graphs, the user determines a manner in which to break the dependencies.

Abstract: A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier or sequence number. The mechanism is placed between a processing element and a memory system such that write data is buffered and information based upon both reads and writes is recorded. Information is maintained allowing the detection of memory conflicts. The packet processor implements a checkpoint repair mechanism allowing processing to restart from defined checkpoints. In some embodiments this is done with sub-sequence numbers. When a memory conflict is detected a restart signal is generated to backup and restart from a given checkpoint.

Abstract: A fractional caching method and an adaptive contents transmitting method using the same are provided. The fractional caching method includes the steps of setting up a divided location for dividing a certain object into two parts, receiving an evict request for acquiring a space in the inside of the cache, when the evict request is transmitted, dividing a plurality of objects stored in the cache into a prefix-Object located in the head of the object and a suffix-Object located in the tail of the object from the divided location, and removing only the suffix-Object of each object, wherein the divided location is set up at a size rate that a size of the prefix-Object is in inverse proportion to the number of the destination types.