Patents Examined by Stephen C. Elmore
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Patent number: 7925840Abstract: The present invention provides a data processing apparatus and method for managing snoop operations. The data processing apparatus has a plurality of processing units for performing data processing operations requiring access to data in shared memory, with at least two of the processing units having a cache associated therewith for storing a subset of the data for access by that processing unit. A snoop-based cache coherency protocol is employed to ensure data accessed by each processing unit is up-to-date, and when an access request is issued the cache coherency protocol is referenced in order to determine whether a snoop process is required. Snoop control storage is provided which defines a plurality of snoop schemes, each snoop scheme defining a series of snoop phases to be performed to implement the snoop process, and each snoop phase requiring a snoop operation to be performed on either a single cache or multiple caches.Type: GrantFiled: September 5, 2008Date of Patent: April 12, 2011Assignee: ARM LimitedInventors: Antony John Harris, Bruce James Mathewson, Christopher William Laycock
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Patent number: 7925828Abstract: According to one embodiment, a disk has a set of tracks thereon. A controller performs refresh control for reading data by a head from a track on the disk to be refreshed and for writing the read data by the head to a spare track adjacent to the track from which the data has been read. The controller switches the track from which the data has been read to a new spare track after the writing.Type: GrantFiled: June 26, 2009Date of Patent: April 12, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Takao Aoki, Yasuhiko Ichikawa
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Patent number: 7925844Abstract: Apparatus, systems, and methods are disclosed that operate to encode register bits to generate encoded bits such that, for pairs of addresses, an encoded bit to be coupled to a first address in a memory device may be exchanged with an encoded bit to be coupled to a second address in the memory device. Apparatus, systems, and methods are disclosed that operate to invert encoded bits in logic circuits in the memory device if original bits were inverted. Additional apparatus, systems, and methods are disclosed.Type: GrantFiled: November 29, 2007Date of Patent: April 12, 2011Assignee: Micron Technology, Inc.Inventor: George Pax
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Patent number: 7921268Abstract: The system and method of the invention provides for function-specific replication of digital data, such as files or objects, with a configurable time delay for each function to be replicated. The system includes a source storage system from which digital data is to be replicated, a destination storage system(s) to which the digital data is being replicated, a replication management module for managing the function specific replication delay and the data replication between the source storage systems and the destination storage system(s).Type: GrantFiled: November 14, 2007Date of Patent: April 5, 2011Inventor: Holger Jakob
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Patent number: 7913056Abstract: A clustered storage array consists of multiple nodes coupled to one or more storage systems. The nodes provide a LUN-device for access by a client. The LUN-device maps to a source logical unit corresponding to areas of storage on the one or more storage systems. A target logical unit corresponds to different areas of storage on the one or more storage systems. The source logical unit is migrated in parallel by the multiple nodes to the target logical unit. Data to be copied from the source logical unit to the target logical unit are grouped into data chunks. Two or more of the plurality of nodes concurrently attempt to acquire an exclusive lock for a set of data chunks. The node acquiring the exclusive lock migrates the set of data chunks from the source logical unit to the target logical unit, while the exclusive lock is used to prevent other nodes from migrating the set of data chunks.Type: GrantFiled: January 28, 2008Date of Patent: March 22, 2011Assignee: EMC CorporationInventors: Michael F. Brown, Kiran P. Madnani, David W. DesRoches
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Patent number: 7904635Abstract: The present invention provides a method of data management for a flash memory medium, characterized in that the status flag of the memory block of said flash memory medium is set as an unfinished state during operating the memory block; after finishing the manipulation, the status flag is set from the unfinished to a finished state. This method ensures that the original data in the flash memory medium will not be lost even if the false power cut occurs when writing the data into the flash memory medium. The present invention also provides a method of writing and a method of recovering the data in the flash memory medium using the above-mentioned data management method.Type: GrantFiled: February 26, 2004Date of Patent: March 8, 2011Assignee: Netac Technology Co., Ltd.Inventors: Guoshun Deng, Xiaohua Cheng, Feng Xiang
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Patent number: 7904677Abstract: A memory control device that can improve the speed of a memory interface. A packet disassembly section disassembles packet data into segments and detects packet quality information. A memory management section has an address management table and manages a state in which the packet data is stored according to the packet quality information. A segment/request information disassembler disassembles the segments into data by an access unit by which memories can be written/read, and generates write requests and read requests according to the access unit. A memory access controller avoids a bank access to which is prohibited because of a bank constraint, extracts a write request or a read request corresponding to an accessible bank from the write requests or the read requests generated, and gains write/read access to the memories.Type: GrantFiled: August 26, 2008Date of Patent: March 8, 2011Assignee: Fujitsu LimitedInventors: Hidenori Sugai, Hiroshi Tomonaga, Satoshi Nemoto
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Patent number: 7904654Abstract: A disk storage system containing a storage device having a record medium for holding the data, a plurality of storage sub-systems having a controller for controlling the storage device, a first interface node coupled to a computer using the data stored in the plurality of storage sub-systems, a plurality of second interface nodes connected to the storage sub-systems, a switch connecting to a first interface node and a plurality of second interface nodes to perform frame transfer therebetween based on node address information added to the frame. The first interface node has a configuration table to store structural information for the memory storage system and in response to the frame sent from the computer, analyzes the applicable frame, converts information relating to the transfer destination of that frame based on structural information held in the configuration table, and transfers that frame to the switch.Type: GrantFiled: September 17, 2009Date of Patent: March 8, 2011Assignee: Hitachi, Ltd.Inventors: Naoto Matsunami, Takashi Oeda, Akira Yamamoto, Yasuyuki Mimatsu, Masahiko Sato
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Patent number: 7895391Abstract: A method for writing an audio/video information stream to an optical disc, and for reading the information from disc. The information stream includes alternative video parts which are recorded in an interleaved manner; an interleaved unit includes angle blocks, each angle block including one portion of each of the alternative video stream parts. For each video portion, entry points are defined. A user is allowed to change from one video stream to another video stream at any moment during the playback of a video portion; the change will be effected at the first entry point after the user command. Thus, it is not necessary to wait until the video portion has been completely played back; thus, it is possible to define large angle block lengths, so that during normal play the jump frequency is reduced.Type: GrantFiled: December 16, 2004Date of Patent: February 22, 2011Assignee: Koninklijke Philips Electronics N.V.Inventor: Wilhelmus Jacobus Van Gestel
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Patent number: 7890701Abstract: A method and system for dynamic distributed data caching includes providing a cache community of peer members and a master member. A master member volunteers to leave the cache community upon which decision a peer member is selected to become the new master member. Each peer member has an associated first content portion indicating content to be cached by the respective peer. A client may be allowed to join the cache community. A peer list associated with the cache community is updated to include the client. The peer list indicates the peers in the cache community. A respective second content portion is associated with each peer based on the addition of the client.Type: GrantFiled: June 1, 2010Date of Patent: February 15, 2011Assignee: Parallel Networks, LLCInventors: Keith A. Lowery, Bryan S. Chin, David A. Consolver, Gregg A. DeMasters
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Patent number: 7882311Abstract: Techniques that may utilize generic tracker structures to provide data coherency in a multi-node system that supports non-snoop read and write operations. The trackers may be organized as a two-dimensional queue structure that may be utilized to resolve conflicting read and/or write operations. Multiple queues having differing associated priorities may be utilized.Type: GrantFiled: February 11, 2010Date of Patent: February 1, 2011Assignee: Intel CorporationInventors: Aimee D Wood, Robert J. Safranek
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Patent number: 7882310Abstract: Methods and apparatus provide for associating memory allocation table (MAT) entries with nodes in a binary tree such that the nodes and the entries are grouped into hierarchical levels, each entry including status information; associating the nodes and the entries with segments of a shared memory of a multi-processor system such that higher level nodes and entries are associated with larger numbers of segments of the shared memory and lower level nodes and entries are associated with smaller numbers of segments of the shared memory; initializing the MAT such that the status information of at least a plurality of entries indicates that the associated segment or segments of the shared memory are available for reservation; and selecting one entry in a group of entries in the MAT at a level corresponding to a desired size of the shared memory to be reserved.Type: GrantFiled: May 1, 2008Date of Patent: February 1, 2011Assignee: Sony Computer Entertainment Inc.Inventors: Keisuke Inoue, Masahiro Yasue
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Patent number: 7882313Abstract: A data recording system comprises a first memory, a counting unit for counting the number of data writes to the first memory, and an alarm unit for outputting an alarm if the number of data writes to the first memory reaches a first threshold value. The counting unit writes data of the number of writes, which represents the number of data writes to the first memory, to the first memory or a second memory. The alarm unit outputs an alarm based on the data of the number of writes, which is written to the first or the second memory.Type: GrantFiled: November 29, 2007Date of Patent: February 1, 2011Assignee: Fujitsu LimitedInventor: Nobuhiro Rikitake
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Patent number: 7877562Abstract: A flash memory stores a boot program of a host system and its backup program. A memory controller determines whether or not the boot program is stored properly in the flash memory when the host system is to be activated. The memory controller reads out the boot program in a case where the boot program is stored properly, and reads out the backup program in a case where the boot program is not stored properly. Then, the memory controller supplies the read-out boot program or backup program to the host system. This makes it possible to avoid a situation that the host system cannot be activated due to the boot program not being able to be executed.Type: GrantFiled: June 13, 2006Date of Patent: January 25, 2011Assignee: TDK CorporationInventor: Naoki Mukaida
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Patent number: 7877545Abstract: A technique is provided for implementing online restriping of a volume in a storage area network. A first instance of the volume is instantiated at a first port of the fibre channel fabric for enabling I/O operations to be performed at the volume. While restriping operations are being performed at the volume, the first port is able to concurrently perform I/O operations at the volume.Type: GrantFiled: September 8, 2008Date of Patent: January 25, 2011Assignee: Cisco Technology, Inc.Inventors: Samar Sharma, Dinesh Dutt, Sanjaya Kumar, Umesh Mahajan, Thomas J. Edsall
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Patent number: 7877572Abstract: Apparatus and method are described for a data processing device. The data processor includes features suitable for executing a software virtual machine. The data processor provides an instruction set that supports object-level memory protection suitable for high speed operation. Memory control logic is provided to accommodate a configuration having relatively less random access memory (RAM) as compared to re-programmable, nonvolatile memory, and to improve access to the re-programmable, nonvolatile memory.Type: GrantFiled: August 6, 2008Date of Patent: January 25, 2011Assignee: Renesas Technology America, Inc.Inventors: Toshiyasu Morita, Shumpei Kawasaki
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Patent number: 7873797Abstract: The present invention relates to a memory controller for an IC with an external DRAM, where the external DRAM has at least one memory bank and communicates with the IC via at least one channel. In line with the invention, the memory controller has a command scheduler which prioritizes the transmission of memory bank commands on the basis of a static priority allocation for commands and a dynamic priority allocation for channels.Type: GrantFiled: November 15, 2004Date of Patent: January 18, 2011Assignee: Thomson LicensingInventors: Tim Niggemeier, Thomas Brune, Lothar Freissmann
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Patent number: 7870348Abstract: A processing device disclosed herein comprises: a memory access circuit which accesses a memory and sequentially reads data from the memory based on a predetermined access pattern; storage in which the data read by the memory access circuit is stored, wherein the memory access circuit sequentially reads the data from the memory and stores the data in storage until storage is full; and a processor which acquires the data from storage.Type: GrantFiled: March 26, 2007Date of Patent: January 11, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Shuou Nomura
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Patent number: 7870347Abstract: The disclosed data processing system comprises a memory means (SDRAM), a plurality of data processing means (IP) provided for accessing to said memory means (SDRAM), and a communication interface means coupled between said memory means (SDRAM) and said plurality of data processing means (IP), said communication interface means including a network of nodes (H 11, H 12, H2), each node comprising at least one slave port (s) for receiving a memory access request from a data processing means (IP) or from a previous node and at least one master port (m) for issuing a memory access request to a next node or to said memory means (SDRAM) in accordance with the memory access request received at said slave port (s), wherein said at least one slave port (s) is connected to a master port (m) of a previous node or to one of said data processing means (IP) and said at least one master port (m) is connected to a slave port (s) of a next node or to said memory means (SDRAM).Type: GrantFiled: August 19, 2004Date of Patent: January 11, 2011Assignee: Koninklijke Philips Electronics N.V.Inventors: Pieter Van Der Wolf, Josephus Theodorus Johannes Van Eijndhoven, Johannes Boonstra
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Patent number: 7870355Abstract: Performing data management operations on replicated data in a computer network. Log entries are generated for data management operations of an application executing on a source system. Consistency point entries are used to indicate a time of a known good, or recoverable, state of the application. A destination system is configured to process a copy of the log and consistency point entries to replicate data in a replication volume, the replicated data being a copy of the application data on the source system. When the replicated data represents a known good state of the application, as determined by the consistency point entries, the destination system(s) may perform a storage operation (e.g., snapshot, backup) to copy the replicated data and to logically associate the copied data with a time information (e.g., time stamp) indicative of the source system time when the application was in the known good state.Type: GrantFiled: December 18, 2006Date of Patent: January 11, 2011Assignee: CommVault Systems, Inc.Inventor: Andrei Erofeev