Abstract: A memory is provided which simplifies the manufacturing process on the supplier side while satisfying specifications provided from the user side. An address space of a memory core includes an information storage region, a code region, and a no-write region. The information storage region includes a first region where no-write region information is written and a second region where a fixed value is written. Program code is written in the code region. The no-write region information indicates the position of the no-write region, and the fixed value indicates a fixed value that is intended to be written to the no-write region. The ROM selects between the fixed value and original read data that is obtained by a data selecting section directly from the memory core, and outputs the selected one as read data.

Abstract: Circuits, methods, and apparatus for FIFO memories made up of multiple local memory arrays. These embodiments limit the number and length of interconnect lines that are necessary to join two or more local memory arrays into a single, larger functional unit. One exemplary embodiment of the present invention provides a FIFO made up of a number of FIFO sub-blocks connected in series. Each FIFO sub-block includes local read and write address counters such that read and write addresses are not bused between the FIFO sub-blocks.

Abstract: A memory module having a board and a plurality of memory elements on the board which belong to different memory ranks, each memory rank being addressable via a respective selection signal. The memory module additionally includes a memory buffer having a memory rank interface coupled to the memory elements of each memory rank, and a selection signal output for the selection signal of each memory rank, the memory elements being arranged in rows on the board and the memory elements of a memory rank extending only over half of the rows.

Abstract: A storage apparatus and an accessing method for the storage apparatus are provided. The storage apparatus comprises a plurality of data blocks, a plurality of spare blocks, and a calculation apparatus. The calculation apparatus is configured to (1) confirm whether a written block has to be updated, (2) select one of the spare blocks as the first moving block, (3) select one of the data blocks as second moving block, (4) store the first data of the second moving block into the first moving block, and (5) store the second data related to the written block into the second moving block. By updating a written block, data stored in other blocks are moved between each other. Blocks are charged and discharged so that data in the blocks are more accurate. The lifetime of the storage apparatus can be increased as well.

Abstract: A method for storing customer data at a non-volatile storage (NVS) at a storage server. A track buffer is maintained for identifying first and second sets of segments that are allocated in the NVS. A flag in the track buffer identifies which of the first and second sets of segments to use for storing customer data for which a write request has been made. The customer data is stored in the NVS in successive commit processes. Following a power loss in the storage server, the NVS uses the track buffer information to identify which of the first and second sets of segments was involved in the current commit process to allow the current commit process to be completed.

Abstract: A computer comprising a processor, a volatile main store, a non-volatile random access memory (NVRAM) mirror store, and optionally a cache for the non-volatile mirror store. While programs of the computer are operational, the contents of the volatile main store are mirrored in the non-volatile mirror store such that when a startup signal is received, the contents of the volatile main store are quickly restored from the contents of the non-volatile mirror store.

Abstract: System-directed checkpointing is enabled in otherwise standard computers through relatively straightforward augmentations to the computer's memory controller hub.

Abstract: Computer systems with direct updating of cache (e.g., primary L1 cache) memories of a processor, such as a central processing unit (CPU) or graphics processing unit (GPU). Special addresses are reserved for high speed memory. Memory access requests involving these reserved addresses are routed directly to the high speed memory. Memory access requests not involving these reserved addresses are routed to memory external to the processor.

Abstract: Reclamation of an Erase Unit of a flash memory is performed concurrently with a file operation on the flash memory by initiating a reclamation operation on the individually erasable portion of the memory, by suspending the reclamation operation for the file operation, by performing the file operation, and by resuming the reclamation operation.

Abstract: An integrated circuit is provided with at least one processing unit (TM), a cache memory (L2 BANK) having a plurality of memory modules, and remapping means (RM) for performing an unrestricted remapping within said plurality of memory modules. Accordingly, faulty modules can be remapped without limitations in order to optimise the utilization of the memory modules by providing an even distribution of the faulty modules.

Abstract: A system and method of using an n-way cache are disclosed. In an embodiment, a method includes determining a first way of a first instruction stored in a cache and storing the first way in a list of ways. The method also includes determining a second way of a second instruction stored in the cache and storing the second way in the list of ways. In an embodiment, the first way may be used to access a first cache line containing the first instruction and the second way may be used to access a second cache line containing the second instruction.

Abstract: A method for dynamically allocating control of a storage device, the method comprising receiving an access request from a first computer requesting access to a storage device; directing, based upon the access request, a first storage controller computer to assume an inactive state with respect to control of the storage device; and directing, based upon the access request, a second storage controller computer to assume an active state with respect to control of the storage device.

Abstract: A method is described for reading out sensor data from an intermediate memory written by at least one sensor to the intermediate memory at a data-transfer rate (Tpas). A sampling rate (Tsg) is selected in such a way as to avoid an overflow of the intermediate memory and all buffered sensor data is read into a control unit memory at the predetermined sampling rate (Tsg), the intermediate memory generating a message (RBE) if no new sensor data is present in the intermediate memory at the time of sampling.

Abstract: A method and system for promoting a snapshot in a distributed striped volume system is provided. A master volume server is configured with a rollback process such that when it is determined that a rollback is required, the master volume server sets a flag persistently in its own raid label on disk. After the persistent flag is set, the master volume server determines a “common snapshot,” and starts the process of sending RPC messages to each node hosting constituent volumes instructing each constituent volume to roll back to the identified snapshot. When the nodes receive this message a flag is set in the own raid label of each constituent volume and the volume then promotes the particular snapshot. If the master volume server has not received a successful response from each node that the snapshot promotion was successful within a specified time period, there is a retry. The common snapshot is then used as the active file system, thus providing data recovery for the striped volume set.

Abstract: A system calculates the optimal allocation of two or more resources provided by a resource provider to a task within a computer system from a plurality of possible allocations. In doing so, the system calculates the total volume of an N-dimensional cube, where N is the number of resources provided by the resource provider, representing the respective amounts of resources available to be allocated. The system also calculates the average volume of the N?1 dimensional shapes forming the sides of the N-dimensional cube. The system then calculates, at least partly from the ratio of the total volume to the average volume, the balance resulting from the allocation of resources represented by the N-dimensional cube. The system then calculates the imbalance resulting from the allocation of resources at least partly from the balance and determines the smallest imbalance as the optimal allocation of resources.

Abstract: The present invention discloses methods for an application, running on a host system, to access a restricted area of a storage device, the method including the steps of: providing a file system for running on the host system; restricting access, by the file system, to the restricted area; sending an indication, from the application to the storage device, that data being sent by the application to the storage device via the file system is intended for the restricted area; detecting the indication in the storage device; and making the data, residing in the restricted area, available for reading by the application upon receiving an application request. Preferably, the method further includes the step of: releasing wasted areas, of the storage device, for use by the file system. Preferably, the method further includes the step of: copying non-restricted data from a non-restricted area into the restricted area.

Abstract: Transactional memory (TM) may be used in conjunction with various synchronization mechanisms, such as that copy a current version of an object, update the copy, and then cause the copy to become current atomically by changing a “current version” indicator. Software operations to modify an object may first make a private copy of the object, modify the private copy, and atomically make the private copy the current version while verifying that no other software operation or transaction has concurrently updated the object. A transaction may be used to update the current copy of a collection of data “in place” and thereby avoiding the necessity to make a copy of the data being modified. If the transactional memory mechanism is unable to complete the transaction to modify the collection of data in place, a set of software operations may be used to modify the collection of data.

Abstract: Methods and apparatus provide for sending a data command from a first of a plurality of devices to a first address concentrator within a first of a plurality of processing systems; selecting one of the other processing systems, the selected processing system having data addressed by the data command stored therein; sending the data command to a first address concentrator of the selected processing system; and broadcasting the data command from the first address concentrator of the selected processing system to a second address concentrator in each of the processing systems.

Abstract: A memory controller connected to memory includes: an address reception unit for receiving an address code externally input together with a command; and a command conversion unit for outputting to the memory an MRS command to change the internal settings of the memory based on the address code when the address code input together with a first command specifies an address space for which the memory is not implemented.

Abstract: Applications are protected from being exposed to exploits and instabilities due to memory operations involving zero byte allocations. Memory operations involving a zero byte allocation are handled by a zero byte memory manager. When an application requests a zero byte allocation, a pointer to a protected part of memory is returned such that when the application attempts to read and/or write to the location the program flow is interrupted.