Abstract: A method and circuit to implement a match against range rule functionality. A first rule entry and a second rule entry are stored. The first rule entry includes at least two consecutive identical bits. The first rule entry represents a numerical range. A first field of a binary key is compared with the first rule entry to determine whether any of the bits of the first field are not identical. A logical result of the comparison between the first field and the first rule entry is inverted to generate a first comparison result. A second field of the binary key is compared with a second rule entry to generate a second comparison result. The first comparison result is then logically ANDed with the second comparison result to determine whether the binary key falls within the numerical range represented by the first rule entry and matches the second rule entry.

Abstract: An apparatus for managing incremental storage includes a storage pool management module that allocates storage volumes to a virtual volume. Also included is an incremental log corresponding to the virtual volume, which maps virtual addresses to storage addresses. The apparatus may also include a replication module that sends replicated data to the virtual volume and a policy management module that determines allocation criteria for the storage pool management module. In one embodiment, the incremental log includes a lookup table that translates read and write requests to physical addresses on storage volumes within the virtual volume. The replicated data may include incremental snapshot data corresponding to one or more primary volumes. The various embodiments of the virtual incremental storage apparatus, method, and system facilitate dynamic adjustment of the storage capacity of the virtual volume to accommodate changing amounts of storage utilization.

Abstract: Systems and methods for storing stack data for multi-threaded processing in a specialized cache reduce on-chip memory requirements while maintaining low access latency. An on-chip stack cache is used store a predetermined number of stack entries for a thread. When additional entries are needed for the thread, entries stored in the stack cache are spilled, i.e., moved, to remote memory. As entries are popped off the on-chip stack cache, spilled entries are restored from the remote memory. The spilling and restoring processes may be performed while the on-chip stack cache is accessed. Therefore, a large stack size is supported using a smaller amount of die area than that needed to store the entire large stack on-chip. The large stack may be accessed without incurring the latency of reading and writing to remote memory since the stack cache is preemptively spilled and restored.

Abstract: Embodiments may comprise logic such as hardware and/or code within a heterogeneous multi-core processor or the like to coordinate reading from and writing to buffers substantially simultaneously. Many embodiments include multi-buffering logic for implementing a procedure for a processing unit of a specialized processing element. The multi-buffering logic may instruct a direct memory access controller of the specialized processing element to read data from some memory location and store the data in a first buffer. The specialized processing element can then process data in the second buffer and, thereafter, the multi-buffering logic can block read access to the first buffer until the direct memory access controller indicates that the read from the memory location is complete. In such embodiments, the multi-buffering logic may then instruct the direct memory access controller to write the processed data to other memory.

Abstract: This invention provides a user or an operator with a management apparatus or method for displaying logical connection information between an interface connected to a computer and a switch and a storage system or a logical unit in the storage system in a virtual storage system, wherein the switch receives a first access request from said computer, converts said first access request to a second access request to one of said plural storage systems, and sends said second access request to one of said plural storage systems or one logical unit.

Abstract: An approach for de-fragmenting physical memory generally involves grouping kernel pages together based on large pages. The de-fragmentation procedure is triggered, such as by a kernel page-freelist being empty. The first user page from a user page-freelist is selected, marked as a kernel page (e.g., by setting a P_KERNEL bit), added to the kernel page-freelist, and then the large page in which the selected page is identified. Starting with the first small page within the large page, the small pages are processed by the de-fragmentation procedure, resulting in as many small pages as possible being marked as kernel pages and then added to the kernel page-freelist. Later, when a large page is coalesced, the number of kernel pages that must be relocated within the large page being coalesced is reduced or eliminated as a result of the de-fragmentation of the physical memory.

Abstract: A method, system, apparatus, and computer-readable medium are provided for improving storage in a disk array are provided. According to aspects of the invention, a redundant disk array is combined with a mechanism for thin provisioning of the array. Thin provisioning refers to a process of allocating physical capacity to logical volumes on an as-needed basis. Data structures containing a mapping between the logical location of stored data and its actual location on a physical device are maintained. Through the use of the thin provisioning mechanism, physical storage space can be allocated sequentially, regardless of the order of logical writes. In this manner, the data stored on the array grows in a linear manner. The data structures maintained by the thin provisioning mechanism can be used to identify the portions of a device or an array that have been previously written.

Abstract: A Flash memory system architecture having serially connected Flash memory devices to achieve high speed programming of data. High speed programming of data is achieved by interleaving pages of the data to be programmed amongst the memory devices in the system, such that different pages of data are stored in different memory devices. A memory controller issues program commands for each memory device. As each memory device receives a program command, it either begins a programming operation or passes the command to the next memory device. Therefore, the memory devices in the Flash system sequentially program pages of data one after the other, thereby minimizing delay in programming each page of data into the Flash memory system. The memory controller can execute a wear leveling algorithm to maximize the endurance of each memory device, or to optimize programming performance and endurance for data of any size.

Abstract: A garbage collection apparatus and a method using the same are disclosed. The garbage collection method comprises: making a list of objects that must be deleted from a memory; calculating a predetermined residual time for responding to an external command; deleting the listed objects from the memory during the residual time; and storing a list of remaining objects that have not been deleted from the memory during the residual time. Accordingly, communication failure due to a response delay or timeout is prevented by distributed processing loads of garbage collection.

Abstract: In an information processing apparatus of this invention having a cache memory, a TLB and a TSB, a second retrieval unit retrieves a second physical address from an address translation buffer by using a second virtual address corresponding one-to-one to a first virtual address, and a prefetch controller enters a first address translation pair of the first virtual address from an address translation table into a cache memory by using a second physical address which is a result of the retrieval, thereby largely shortening the processing time of a memory access when a TLB miss occurs at the time of the memory access.

Abstract: An information handling system includes a processor having access to a system memory. The system is operable to detect a thermal alert and identify an associated portion of system memory. The system may then modify memory allocation information used by an operating system to allocate system memory. When the thermal alert indicates a rising memory module temperature that exceeds a specified threshold, the modification of the memory allocation information causes the memory to appear to be more “distant” from the system processor(s) and thereby allocated less preferentially than other memory. If the temperature continues to rise beyond a higher threshold, a second modification of the memory allocation information is performed to simulate a “hot eject” of the memory module. As the memory module cools, the memory allocation information can be restored to simulate a hot add of the memory module and to restore the proximity of the memory module.

Abstract: A memory architecture includes at least one unbuffered dual inline memory module (DIMM). At least one advanced memory buffer (AMB) provides an interface between the at least one DIMM and a host memory controller.

Abstract: The present invention relates to a memory on a silicon microchip, having a serial input/output, an integrated memory array addressable under N bits, and at least one register that is read accessible, after applying a command for reading the register to the memory. The memory stores a most significant address allocated to the memory within an extended memory array wherein the memory is incorporated or intended to be incorporated. A master memory signal is generated based on the most significant address allocated to the memory. A central processing unit executes a command for reading the register and supplies the content of the register to the serial input/output of the memory only if the memory is the master memory within the extended memory array. The memory includes slave memories whose operation depends upon the read/write status of the master memory.

Abstract: One embodiment includes a system comprising a processor configured to read and write data packets via a data bus to and from at least one additional hardware device. The system also comprises a data buffer configured to store a plurality of consecutive related flits associated with at least one of the data packets in one of a plurality of addressable locations of the data buffer. The system further comprises a pointer memory configured to store a respective pointer associated with each of the plurality of addressable locations of the data buffer.

Abstract: A storage device is provided. The storage device includes a memory that includes interleaved fast and slow pages and a controller. In response to a command from a host of the storage device the controller stores fast-reading data in the memory. If the fast and slow pages alternate, the controller stores the fast-reading data in the first pages alternately with filler data in the low pages, and if contiguous pluralities of the fast and slow pages alternate, the controller stores the fast reading data in the contiguous pluralities of the fast pages alternately with the filler data in the contiguous pluralities of the slow pages.

Abstract: A system and method to provide injection of important data directly into a processor's cache location when that processor has previously indicated interest in the data. The memory subsystem at a target processor will determine if the memory address of data to be written to a memory location associated with the target processor is found in a processor cache of the target processor. If it is determined that the memory address is found in a target processor's cache, the data will be directly written to that cache at the same time that the data is being provided to a location in main memory.

Abstract: A cache on-demand module employing a cache performance module for managing size adjustments to a cache size of a cache memory in view of supporting an optimal performance of a storage subsystem employing the cache memory by determining an optimal cache size of the cache memory for supporting the optimal performance of the storage subsystem, and reporting any size adjustment to the cache size of the cache memory based on the determined optimal cache size of the cache memory. The cache on-demand module further employs a cache accounting module for managing a client expense account associated with the cache memory by determining whether a client charge or a client rebate is warranted as a function of any size adjustment to the cache size of the cache memory by the cache performance module.

Abstract: A storage emulator and method thereof are disclosed. The storage emulator allows a host system to access a storage unit connected to a storage system as if the storage unit is directly coupled to the host system. The storage emulator includes a virtual storage emulating module, a storage-managing unit, and a communicating module. The virtual storage emulating module emulates at least one virtual storage unit corresponding to the storage unit on the host system and receives a storage accessing command from the host system. The storage-managing unit identifies the storage accessing command as either a self-sustaining type command or a non-self-sustaining type command. The communicating module communicates with the storage unit of the storage system via the network. If the storage accessing generates a self-sustaining command response in accordance with the storage accessing command and returns the self-sustaining command response to the host system directly.

Abstract: A computerized method for sharing removable storage media in a network, the method comprising associating, in an index entry, a first piece of removable storage media in a first storage device with at least a first storage policy copy and a second storage policy copy; copying, to the first piece of removable storage media, data associated with the first storage policy copy; and copying, to the first piece of removable storage media, data associated with the second storage policy copy.

Abstract: A customizable cache discard policy is provided which reduces adverse consequences of conventional discard policies. In a data processing system, a cache controller invokes a cache data discard policy as the cache approaches its capacity. Using one possible policy, data having the shortest retrieval (fetch) time is discarded before data having longer retrieval times. In an alternative policy, data may be discarded based upon its source. Weightings may be applied based upon the distance from each source to the cache, may be based upon priorities assigned to each source, or may be based upon the type of each source.