Abstract: In a mobile communication system including a transmitter and a receiver, an LDPC code is generated by encoding received information data such that a fifth partial matrix obtained by combining a second partial matrix having even-numbered columns of a first partial matrix corresponding to the information data with a fourth partial matrix having odd-numbered columns of a third partial matrix corresponding to a parity, and an eighth partial matrix obtained by combining a sixth partial matrix having odd-numbered columns of the first partial matrix with a seventh partial matrix having even-numbered columns of the third partial matrix correspond to a ninth partial matrix obtained by exclusive-ORing the first partial matrix and the third partial matrix and a parity check matrix having a predetermined rank in a binary field. A space-time LDPC code is generated by spatial-mapping the LDPC code according to a predetermined spatial mapping scheme.

Abstract: Fast min*? (min-star-minus) or max*? (max-star-minus) circuit in LDPC (Low Density Parity Check) decoder. A novel and efficient approach by which certain of the calculations required to perform check node processing within various types of decoders is presented. The functionality and architectures presented herein are applicable to LDPC decoders and may also be employed within other types of decoders that are operable to decode other types of coded signals as well. The parallel and sometimes simultaneous calculation and determination of certain parts of the overall resultant of the max*? and/or min*? processing allows for very fast operation when compared to prior art approaches.

Abstract: A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM and a 28 bit and a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/Parity register.

Abstract: A transmission apparatus includes a communication unit for performing transmission and reception of encoded data packets with other terminals, a redundant code generating unit for generating a redundant code packet for restoring data lost due to the loss of a data packet, a redundant code control unit for controlling the band used by the redundant code packet, a buffer for accumulating retransmission packets that can be retransmitted when corresponding data are lost, a retrieval unit for retrieving a corresponding retransmission packet from the buffer for retransmission upon receiving a retransmission request for the data packet, a retransmission control unit for controlling the band used for retransmission, and a band control unit for controlling the bandwidth of a redundant code based on the band used for retransmission and the band currently used for the redundant code.

Abstract: A method and apparatus for decoding a coded data stream of bits using an inner decoder, deinterleaver and an outer decoder. The outer decoder first decodes by error correction decoding for r errors per word. The decoding is terminated and a decoded word is outputted if the syndromes of the corrected word of the first decoding are all zeros. If the syndromes of the corrected word of the first decoding are not all zeros, a second decoding is performed by error decoding and erasure for the number of errors reduced by one and the number of erasures increased to two. The decoding is terminated and a decoded word is outputted if the syndromes of the corrected word of the second decoding are all zeros. If the syndromes of the corrected word of the second decoding are not all zeros, the second decoding by correcting and erasure decoding is repeated for the number of errors reduced by one and the number of erasures increased by two for each iteration of the second decoding.

Abstract: A data processing apparatus capable of preventing contention of memory access between the HARQ synthesis and rate dematching in the HARQ processing using two or more single-port memories is provided. A buffer includes two physical memories. One of the physical memories is used as an even address memory, and the other is used as an odd address memory. With respect to access to the buffer conducted by the HARQ synthesis and rate dematching, access control is conducted so as to make the rate dematching access the odd address memory when the HARQ synthesis accesses the even address memory.

Abstract: The present invention is directed to a data recording method of notifying degree of deterioration of recording medium thus to perform stable recording operation. Even in the case where uncorrectable address read error does not exist, deterioration information is displayed in accordance with generated and stored deterioration information. Whether or not address read error of ATIP is detected over successive two frames or more, or whether or not four errors or more are detected on the average at 75 frames is discriminated. In the case where error detecting state is adapted to affirmative discrimination condition, warning is displayed. In the case where 200 errors or more detected from deterioration information generated in processing with respect to random missing with respect to written data exist on the average with respect to successive 750 frames, or in the case where one error or more detected in processing with respect to random missing exist, disc deterioration warning display is similarly performed.

Abstract: A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM and a 28 bit and a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/Parity register.

Abstract: A digital content transmission and reception system that uses feedback and retransmission of missing content is described. A content transmission system broadcasts a complete set of digital content to a plurality of content reception systems via a communication link. A content reception system receives a corresponding incomplete set of digital content, determines particular content portions that are missing, and provided feedback indicating the missing content portions to the content distribution system. The content distribution system then re-transmits content based on the feedback.

Abstract: A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card provided with a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM, and a 28 bit 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/Parity register.

Abstract: The current invention involves a forward error detection system, especially for use with Low Density Parity Check codes. A parallel SISO structure allows the decoder to process multiple parity equations at the same time. There is a new SISO decoder which allows for the updating of the Log-likelihood-ratios in a single operation, as opposed to the two pass traditionally associated with the Tanner Graphs. In the decoder, there is a mapping structure that correctly aligns the stored estimates, the stored differences and the SISOs. There is also the ability to deal with multiple instances of the same data being processed at the same time. This structure manages the updates and the differences in such a manner that all calculations on a single piece of data that are processed in parallel are incorporated correctly in the new updated estimates.

Abstract: A memory system with transparent error correction circuitry provides full stuck-at fault coverage for both test data patterns and the corresponding error correction code (ECC) values. The memory system includes a semiconductor memory having a memory array, a memory interface and an error detection/correction unit. The memory array is configured to store test data patterns and corresponding error correction code (ECC) values. The memory interface is configured such that the ECC values are not directly accessible. The error detection/correction unit is configured to correct single-bit errors in the test data patterns and corresponding ECC values. A set of test data patterns associated with the semiconductor memory is selected such that any multiple-bit error in a test data pattern and the corresponding ECC value causes the error detection/correction unit to provide an output data pattern having an error, thereby rendering multiple-bit faults 100% detectable.

Abstract: A method of recording data as presence/absence of marks on an information recording medium includes a step of obtaining data pieces, each of which has size of one block and is made by adding error-correction-purpose data to information data, a step of attaching to each of the data pieces a synchronizing signal that includes a portion having the marks and a portion having no mark, a step of recording the data pieces on the information recording medium in units of the one block inclusive of the synchronizing signal, and a step of placing a concatenation point at a predetermined position within the synchronizing signal when adding, or writing in an overwriting manner, the data pieces in units of the one block, the concatenation point defining a position at which said adding or said writing starts.

Abstract: A reduced complexity turbo decoding scheme combines elements from two MAP (Maximum a posteriori) algorithms, namely a LogMAP algorithm and a max-LogMAP algorithm. Forward and backward recursive metrics are computed in accordance with the max-LogMAP algorithm, while output extrinsic LLR (Log Likelihood Ratio) values are computed in accordance with the LogMAP algorithm.

Abstract: An apparatus and method for encoding low-density parity check codes. Together with a repeater, an interleaver and an accumulator, the apparatus comprises a precoder, thus forming accumulate-repeat-accumulate (ARA codes). Protographs representing various types of ARA codes, including AR3A, AR4A and ARJA codes, are described. High performance is obtained when compared to the performance of current repeat-accumulate (RA) or irregular-repeat-accumulate (IRA) codes.

Abstract: A processor on which a software-based interleaver is run performs interleaver generation, which is split into two parts to reduce the overhead time of interleaver changing. First, preprocessing prepares seed variables, requiring a small memory. Second, on-the-fly address generation generates interleaved addresses through simple adding and subtracting operations using the seed variables.

Abstract: A method, adapted to a 3GPP turbo coder, for interleaving a plurality of data of a data frame and a circuit thereof is provided. The present invention computes a value of Row Parameter according to the size of the data frame, computes an index for a table according to the value of Row Parameter, and searches for a value of Column Parameter, a value of Prime Parameter and a value of Primitive Parameter from the table.

Abstract: An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value.

Abstract: New and improved a-posteriori decoding probabilities, decisioning metrics, and implementation algorithms for turbo and convolutional decoding to replace the probabilities and decisioning metrics currently used in the maximum likelihood ML and maximum a-posteriori MAP algorithms. A-posteriori probabilities p(x}y) replace the current ML probabilities p(y}x) wherein y is the received symbol and x is the transmitted data and the MAP a-posteriori probability p(s?,s|y) replaces the current MAP joint probability p(s?,s,y) wherein s?,s are the trellis decoding states at k?1, k and y is the observed data set y(k),k=1, 2, . . . , N. This yields a-posteriori probabilities and decisioning metrics to improve decisioning and bit error rate BER performance and to provide a new mathematical decoding framework. Complexity is the same as current implementations.

Abstract: In accordance with an embodiment of the present invention, a Viterbi decoder is described that operates on convolutional error correcting codes. The decoder allows for a pipelined architecture and a unique partitioning of survivor memory to maintain data integrity. Throughput rate is improved and stalling minimized by accessing memory words using a look-ahead function to fill the pipeline.