Abstract: A detection and recovery mechanism is herein disclosed for soft errors corrupting TLB data. The mechanism works with a hardware page walker (HPW) and instruction steering control mechanisms in a processor to provide soft error recovery in the TLB arrays and latches. Through use of the disclosed detection and recovery mechanism, efficient and robust protection from silent data corruption is provided without requiring more expensive built-in redundancy.

Abstract: An apparatus, a carrier medium storing instructions to implement a method, and a method in a node of a wireless network able to receive packets that exactly or substantially conform to a wireless network standard according to which each packet includes a header having bits that have respective correct values in the case that the packet exactly conforms to the standard. The method includes receiving a start-of-packet (SOP) trigger that indicates that a packet may have been received, checking one or more bits in the header to determine whether or not they have their respective correct values, and continuing to process the packet in the case that the checking indicates that the checked bits have their respective correct values. In one implementation, the header includes a first field modulated at a known rate that has one or more reserved bit locations, and a second field modulated at a data rate indicated in the first field.

Abstract: An encoder uses output symbol subsymbols to effect or control a tradeoff of computational effort and overhead efficiency to, for example, greatly reduce computational effort for the cost of a small amount of overhead efficiency. An encoder reads an ordered plurality of input symbols, comprising an input file or input stream, and produces output subsymbol. The ordered plurality of input symbols are each selected from an input alphabet, and the generated output subsymbols comprise selections among an output subsymbol alphabet. An output subsymbol is generated using a function evaluator applied to subsymbols of the input symbols. The encoder may be called one or more times, each time producing an output subsymbol. Output subsymbols can then be assembled into output symbols and transmitted to their destination.

Abstract: Efficient design to implement LDPC decoder. The efficient design presented herein provides for a solution that is much easier, smaller, and has less complexity than other possible solutions. The use of a ping-pong memory structure (or pseudo-dual port memory structure) in conjunction with a metric generator near the decoder's front end allows parallel bit/check node processing. An intelligently operating barrel shifter operates with a message passing memory that is operable to store updated edges messages with respect to check nodes as well as updated edges messages with respect to bit nodes. Using an efficient addressing scheme allows the same memory structure to store the two types of edges messages with respect to bit nodes: (1) corresponding to information bits and (2) corresponding to parity bits. In addition, an intelligently designed hardware macro block may be instantiated a number of times into the decoder design to support ever greater design efficiency.

Abstract: A method for transmitting variable length packets based on FEC coding. Data packets are successively and contiguously stored in a two-dimensional storage device. FEC coding is performed to generate parity packets. The parity packets are stored in the two-dimensional storage device. The data packets, offsets representing positions of the data packets in the two-dimensional storage device, types of packets, and the parity packets are then transmitted.

Abstract: An electronic device under test (DUT) responds to a digital input signal by generating a digital DUT output signal conveying a repetitive digital signal pattern. An apparatus for measuring various characteristics of the DUT output signal includes a trigger generator for generating a series of trigger signal edges in response to selected DUT output signal edges occurring during separate repetitions of the digital signal pattern. The trigger generator can be configured to generate each trigger signal edge in response to the same or a different edge of the digital signal pattern. The apparatus determines when a DUT output signal edge occurs by determining when the DUT output signal rises above or falls below adjustable reference voltages. The apparatus alternatively responds to each trigger signal edge by measuring a period between two different edges of the digital signal pattern and or by repetitively sampling the DUT output signal to determine its state.

Abstract: A method and system for interleaving in a parallel turbo decoder enables the use of economical dual-port memory. According to the method, an incoming coding block is divided into a plurality of sub-blocks (step 1005). Each sub-block is divided into a plurality of windows (step 1010). An inter-window shuffle is then performed within each sub-block (step 1015). Each window is divided into two sub-windows (step 1020). Then an intra-window permutation is performed within each sub-window (step 1025).

Abstract: An information recording medium includes a management area where management information is recorded and a plurality of physical sector areas used to record a plurality of physical sector data blocks, which are generated by combining some data contained in a plurality of ECC blocks.

Abstract: An information recording medium includes a management area where management information is recorded and a plurality of physical sector areas used to record a plurality of physical sector data blocks, which are generated by combining some data contained in a plurality of ECC blocks.

Abstract: The present invention concerns a device (10) for the encoding of information symbols to transmit or to record, and for the correction of errors among the symbols received or read, according to codes defined over a Galois field Fq, where q is an integer greater than 2 and equal to a power of a prime number, and in which a set of elements of Fq are considered which are denoted yl(j), where j=1, . . . , R with 1?R?q?1 and l=0, . . . , p?1 with p>1.

Abstract: An information recording medium includes a management area where management information is recorded and a plurality of physical sector areas used to record a plurality of physical sector data blocks, which are generated by combining some data contained in a plurality of ECC blocks.

Abstract: A method, system and article of manufacture for the storing convolution-encoded data on a redundant array of independent storage devices (RAID) is described. The convolution-encoded data comprises error correction coded data to eliminate the need for parity as used in conventional RAID data storage. The number of storage devices may vary to accommodate expansion of storage capacity and provide on demand storage.

Abstract: A low-density parity-check (LDPC) decoder (304) has a memory (308), and a processor (306). The processor is programmed to initialize (202) the LDPC decoder, calculate (204) a probability for each check node, calculate (206) a probability for each bit node, calculate soft decisions, update the bit nodes according to the calculated soft decisions, calculate (208) values from the calculated soft decisions, perform (210) a parity check on the calculated values, update (218) log-likelihood ratios (LLRs) if a bit error is detected in the calculated values, update the bit nodes according to the updated LLRs, and repeat the foregoing post initialization steps.

Abstract: Electronic apparatus such as a cordless phone, the electronic apparatus includes detection means for detecting the error of received data and at least two speech buffers as speech buffers for temporarily storing the received voice data. In case the electronic apparatus is in a position where it can communicate with a repeater and a base unit, the electronic apparatus stores the voice data transmitted from the base unit into one speech buffer and stores voice data transmitted from the repeater into the other speech buffer, and uses the voice data of a lower error rate. This maintains high speech quality. In case the electronic apparatus roams from a second wireless network formed around the repeater to a first wireless network formed around the base unit, smooth roaming is provided without degrading the speech quality by using the voice data of a lower error rate stored in either of the two speech buffers, even when the conversation state is gradually degraded and more errors are detected in the received data.

Abstract: Information signals such as grayscale images or audio signals are represented as a sequence of PCM signal samples. To embed auxiliary data in the least significant bits of the signal, the samples are slightly distorted. There is a so-termed “rate-distortion function” (20) which gives the largest embedding rate R given a certain distortion level D. It appears that the efficiency of prior art embedding schemes such as LSB replacement (21,22) can be improved. The invention discloses such embedding schemes (23,24). According to the invention, the signal is divided into groups of L (L>1) signal samples (x). For each group of signal samples, a vector of least significant portions (x mod n) of the signal samples is created. For n=2, the vector comprises the least significant bit of each signal sample. The syndrome of said vector (as defined in the field of error detection and correction) represents the embedded data.

Abstract: Write check bits are generated in a predictive manner for partial-word write transactions in a memory system implementing error code correction. A read data word and associated read check bits are read from an address of the memory. If an error exists in a byte of the read data word, this byte is identified. At the same time, one or more bytes of the uncorrected read data word are merged with one or more bytes of a write data word, thereby creating a merged data word. Write check bits are generated in response to the merged data word. If the merged data word includes a byte of the read data word, which contains an error, the write check bits are modified to reflect this error. The merged data word and the modified (or unmodified) write check bits are then written to the address of the memory.

Abstract: At the receiver in a wireless communications system, the likelihood of a false CRC pass that can occur when a weak received signal produces an all ZERO output from a convolutional or a turbo decoder is minimized. To prevent an all ZERO output, a convolutional decoder selects from among those determined equally most likely transmitted sequences of bits in a data block one that has a weight greater than the one having the minimum weight. A turbo decoder selects a ONE rather than a ZERO as the value of a transmitted bit in a data block when for that bit a bit value of a ZERO and a ONE are determined to be equally likely.

Abstract: A computer system (10) and method are presented for performing ECC corrections on data contained in a mass data storage device (20). The computer system (10) has a host computer (12) having a CPU (14) and an associated mass data storage device (20). At least some ECC hardware is associated with the mass data storage device (25). A device driver (18) is associated with the host computer (12), which includes software instructions for execution by the CPU (14) for performing at least some ECC functions or instructions on data read from the mass data storage device (20).

Abstract: A concatenated equalizer/trellis decoding system for use in processing a High Definition Television signal. The re-encoded trellis decoder output, rather than the equalizer output, is used as an input to the feedback filter of the decision feedback equalizer. Hard or soft decision trellis decoding may be applied. In order to account for the latency associated with trellis decoding and the presence of twelve interleaved decoders, feedback from the trellis decoder to the equalizer is performed by replicating the trellis decoder and equalizer hardware in a module that can be cascaded in as many stages as needed to achieve the desired balance between complexity and performance. The present system offers an improvement of between 0.6 and 1.9 decibels. Cascading of two modules is usually sufficient to achieve most of the potential performance improvement.

Abstract: Data is read from a memory array. Before being stored in a data buffer, a Hamming code detection operation and a Reed-Solomon code detection operation are operated in parallel to determine if the data word has any errors. The results of the parallel detection operations are communicated to a controller circuit. If an error is present that can be corrected by the Hamming code correction operation, this is performed and the Reed-Solomon code detection operation is performed on the corrected word. If the error is uncorrectable by the Hamming code, the Reed-Solomon code correction operation is performed on the word.