Abstract: In a coding system wherein an error correction/detection coding is combined with a synchronization recovering technique using a synchronization code, the problems of a pseudo synchronization and a step out due to error detection are solved. There is provided a coding part for coding an input multiplexed code string to an error correcting/detecting code comprising an information bit and a check bit, and code string assembling part for inserting a synchronization code into any one of a plurality of periodically predetermined synchronization code inserting positions in the code string , for arranging the information bit at an optional position in the code string, and for arranging the check bit at a position other than the synchronization code inserting positions in the code string to assemble an output code string.

Abstract: In general, in one aspect, the disclosure describes a method of determining a checksum. The method includes accessing a checksum of the at least the portion of a packet and adjusting the checksum based on a subset of the at least the portion of the packet before and after modification of the subset.

Abstract: An output coding apparatus includes a coder for coding an inputted bitstream to an error correction and/or detection code composed of information bits and check bits; and a bitstream assembling section for assembling an outputted bitstream by inserting a synchronization code at any one of a plurality of synchronization code insertion positions previously determined in the outputted bitstream, arranging the information bits at any desired positions of the bitstream, and by arranging the check bits at positions other than the synchronization code insertion positions in the bitstream. Therefore, when the coding apparatus is combined with a resynchronization method using both an error correction and/or detection code and a synchronization code, it is possible to solve a problem caused by pseudo-synchronization or synchronization-loss pull-out or step-out due to erroneous detection of the synchronization code.

Abstract: A method of detecting address information for an optical recording and/or reproducing apparatus, including: detecting and/or correcting by using the characteristic of a medium when additional data has a specific value with respect to an area of the medium among address area data on the medium, and/or the characteristic of an address that the address increases by specified unit, an error in detected address area data and outputting the result of error detection and/or correction; and providing optimal address information by using the result of the error detection and/or correction.

Abstract: An output coding apparatus includes a coder for coding an inputted bitstream to an error correction and/or detection code composed of information bits and check bits; and a bitstream assembling section for assembling an outputted bitstream by inserting a synchronization code at any one of a plurality of synchronization code insertion positions previously determined in the outputted bitstream, arranging the information bits at any desired positions of the bitstream, and by arranging the check bits at positions other than the synchronization code insertion positions in the bitstream. Therefore, when the coding apparatus is combined with a resynchronization method using both an error correction and/or detection code and a synchronization code, it is possible to solve a problem caused by pseudo-synchronization or synchronization-loss pull-out or step-out due to erroneous detection of the synchronization code.

Abstract: An information reproduction apparatus using maximum likelihood decoding for calculating likelihood of a value of a reproducing signal to a plurality of reference values, the reproducing signal obtained from a recording medium, to decode the reproducing signal on the basis of the likelihood, the apparatus includes a circuit for detecting the reproducing signal from the recording medium, a circuit for detecting the reference values corresponding to a characteristic of the reproducing signal, and a correction circuit for correcting the reproducing signal or the calculated likelihood according to the detected reference values.

Abstract: A write-back cache has error-correction code (ECC) fields storing ECC bits for cache lines. Clean cache lines are re-fetched from memory when an ECC error is detected. Dirty cache lines are corrected using the ECC bits or signal an uncorrectable error. The type of ECC code stored is different for clean and dirty lines. Clean lines use an error-detection code that can detect longer multi-bit errors than the error correction code used by dirty lines. Dirty lines use a correction code that can correct a bit error in the dirty line, while the detection code for clean lines may not be able to correct any errors. Dirty lines' ECC is optimized for correction while clean lines' ECC is optimized for detection. A single-error-correction, double-error-detection (SECDED) code may be used for dirty lines while a triple-error-detection code is used for clean lines.

Abstract: An interleaver address generator is provided with pruning avoidance technology. It anticipates the points in time when incorrect addresses are computed by an IAG, and bypasses these events. It produces a stream of valid, contiguous addresses for all specified code block sizes. A single address computation engine firstly ‘trains’ itself about violating generated addresses (for a related block size) during the initial H1 half-iteration of decoder operation, and then produces a continuous, correct stream of addresses as required by the turbo decoder. Thus regions of pruned addresses are determined, and then training is performed only in these regions. Thus, computation and population of a pruned event table is determined in less than 1/10 the time required to do a conventional style full training. The resulting pruned event table is compressed down to 256 bits.

Abstract: Data communication over a block-coherent channel in a communication system is described. Low-complexity demodulation techniques that allow good performance are described. A dwell, e.g., a set of block coherent symbols transmitted including a known symbol, e.g., a pseudo pilot symbol, are received, demodulated and decoded by a joint decoder/demodulator employing soft inputs, soft outputs, and interleaving of messages. Low-complexity SISO demodulator is suitable for processing pseudo-pilot modulated information corresponding to each of one or more dwells. The low-complexity method achieves good performance when turbo equalization is used. Some decoding and demodulation embodiments include independent phase estimates and updated independent phase estimates following the extrinsic principle to generate soft symbol values and soft bits.

Abstract: When received data is decoded, a CPU stores a value “1”, which is included in a vector obtained by multiplying the received data by a parity check matrix, as the number of parity errors and also stores hard-decision result information corresponding to the number of parity errors in an output candidate information storage area. If the CPU determines that the received data is uncorrectable after the received data is decoded a given number of times, it reads hard-decision result information corresponding to the smallest number of parity errors, which are included in the number of parity errors stored in the output candidate information storage area and outputs it as a decoding result.

Abstract: Methods, circuits, architectures, and systems for error detection in transmitted data. The method generally includes the steps of (a) performing an error checking calculation on the transmitted data and appended error checking code; (b) determining the calculated error checking code state; and (c) if it has a predetermined state, indicating that there is no error in the transmitted data. The circuitry generally comprises (1) an error checking code calculation circuit configured to calculate error checking code on the transmitted data and the appended error checking code; (2) a vector selector configured to select one of a plurality of error checking vectors; and (3) a logic circuit configured to determine the calculated error checking code state and, if it has a predetermined state, indicate that there is no error in the transmitted data. The software generally includes a set of instructions configured to implement or carry out the present method.

Abstract: A method of retransmitting a data frame and a network apparatus using the method are provided. In the method performed in a wireless network, a first network apparatus transmits a data frame requesting a response frame. A second network apparatus determines a type of response frame according to a reception mode of the data frame. The second network apparatus transmits the determined type of response frame to the first network apparatus. The first network apparatus retransmits the data frame according to the type of the response frame transmitted to the first network apparatus.

Abstract: A method of calculating a diagonal interleaved parity word for groups of words sampled from a bus is provided, wherein a predetermined number of words are included in each sampling cycle. The bus carries successive data words that are followed by a control word. At each sampling cycle, diagonal XOR calculations chains are propagated through the words that were sampled. However, if a sampling cycle includes the control word, the words following the control word are assigned to logical zero values. The diagonal XOR calculation chains may then be terminated after processing the words in this sampling cycle to derive an intermediate diagonal parity word. The intermediate diagonal parity word may then be adjusted according to the number of words that were assigned logical zero values to calculate a second diagonal interleaved parity word.

Abstract: An integrated circuit that accesses memory from data lines in multiple word increments having distributed error correction coding circuitry is described. The data lines are selectively coupled to a portion of the memory for a read of data stored in the portion of the memory. The read includes providing in parallel in the multiple word increments the data stored in the portion of the memory. The data lines are selectively tapped to provide the data from the read to flow in parallel in a first direction and in a second direction. The first direction provides the data to the data registers, and the second direction provides the data to be propagated in an error checking matrix of the distributed error correction coding circuitry.

Abstract: A method for transferring data into a data memory using a data protocol is presented. The data memory is an error correction code (ECC) memory or a non-error correction code memory. The data protocol has different frames. When data are written into an ECC memory, the protocol includes a data mask frame in which the data mask bits are replaced by ECC bits. The method is designed such that ECC and non-ECC DRAMs can be established with the same protocol and at least a similar architecture.

Abstract: In a coding system wherein an error correction/detection coding is combined with a synchronization recovering technique using a synchronization code, the problems of a pseudo synchronization and a step out due to error detection are solved. There is provided a coding part for coding an input multiplexed code string to an error correcting/detecting code comprising an information bit and a check bit, and code string assembling part for inserting a synchronization code into any one of a plurality of periodically predetermined synchronization code inserting positions in the code string, for arranging the information bit at an optional position in the code string, and for arranging the check bit at a position other than the synchronization code inserting positions in the code string to assemble an output code string.

Abstract: One or more methods and systems of effectively retrieving data stored in a media of a storage device are presented. The one or more methods and systems are implemented by way of correcting and detecting errors using a multi-stage decoding process. In one embodiment, the storage device comprises a magnetic hard drive. In one embodiment, the system and method applies an encoding/decoding technique that allows error correction and detection to be performed over a number of successive decode stages or processing stages. Use of the system and method increases the maximum number of symbol errors that may be corrected in an encoded codeword, providing an improvement in data recovery.

Abstract: A digital data transmission error checking method and system is proposed, which is designed for use with a data source unit and a data reception unit for providing a error checking function, and which is characterized by the use of an improved checksum algorithm that initially sets a checksum variable to a fixed value and then repetitively increases the value of the checksum value by adding the value of each data unit in the original digital data stream plus the resulted value of an exclusive-OR operation on the previous checksum value and the index number of the current data unit in the original digital data stream. This feature allows the reception side to determine whether there are erroneous bits in the received data stream even if the sequential order of the bytes in the original digital data stream is mistakenly disordered.

Abstract: Methods and apparatus to extract audio codes are disclosed. An example method includes receiving signals on a plurality of channels and ranking the signals based on at least one characteristic of the signals. A first channel from the plurality of channels is selected based upon the ranking of the signals. The example method further include determining whether a first signal on the first channel includes at least one code and extracting the at least one code from the first signal when the first signal includes the at least one code.

Abstract: A system for error correction coding and decoding information is disclosed. In one embodiment, the first and second encoders are each configured to encode the information, wherein the second encoder has a higher capability than the first encoder. First and second decoders are configured to recover the information, wherein the second decoder recovers the information encoded by the second encoder only if the first decoder cannot recover the information.