Abstract: In an apparatus such as a turbo decoding apparatus in which it is necessary to carry out interleave operation and deinterleave operation, there are provided a memory unit (5) and a memory control unit (12) capable of changing data writing order and data reading order with respect to the memory unit (5) depending on whether data is to be interleaved or deinterleaved. With this arrangement, the single unit of memory (5) can function as an interleaver and a deinterleaver, thereby reducing the size and cost the device.

Abstract: A system for adding a redundancy check to an electronic message to discourage tampering and facilitate identification of altered messages provides a communication device for composing message content, a messaging module with a formatting and encoding layer for encoding the message content with header information in a series of message blocks, and an encryption layer for calculating a redundancy check value and inserting the value in one or more locations within the series of message blocks according a rule defined by a characteristic of the message content or the header information, and encrypting the message for delivery to a recipient. Upon receipt, the recipient communication device decrypts the message, extracts the redundancy check value from the message, and compares a calculated redundancy check value with the extracted redundancy check value to determine if the message had been altered before receipt.

Abstract: Data coherence checking apparatus, a redundant array of independent disks (RAID) controller and a storage system having the checking apparatus and a method therefor are proposed. The present invention employs an XOR operation unit and an OR operation unit to check the coherence of data to be checked. The XOR operation unit is used to perform XOR operation on the data to be checked. After the XOR operation unit finishes performing the XOR operation on the data of a processing set, it outputs an XOR operation result to the OR operation unit to perform OR operation so as to obtain a check result.

Abstract: A method of interleaving blocks of indexed data of varying length is disclosed. The method includes the steps of: providing a set of basic Interleavers comprising a family of one or more permutations of the indexed data and having a variable length; selecting one of the basic Interleavers based upon a desired Interleaver length L; and adapting the selected basic Interleaver to produce an Interleaver having the desired Interleaver length L.

Abstract: A computer system configured to enhance data protection. A computer system includes one or more clients, such as processing subsystems and a memory subsystem interconnected via a network. Transactions within the system may involve the separation of data and a corresponding address in both space and time. At various points in the system, operations may be performed which seek to reunite a data and corresponding address, such as a store operation. In order to further ensure the correspondence of data and an address which is to be used in an operation, clients are configured to generate and utilize an additional symbol. The symbol is generated at least in part on an address which corresponds to data. The symbol is then associated with the data and serves to represent the corresponding address. The symbol may then be utilized by various clients within the system to check an address which is proposed to be used in an operation with the data.

Abstract: Data move operations in a memory device are described that enable identification of data errors. Error detection circuitry in the memory device can be operated using parity data or ECC data stored in the memory. Results of the error detection can be accessed by a memory controller for data repair operations by the controller.

Abstract: An apparatus and method interleaving symbols coded by a turbo encoder in a communication system that uses the turbo encoder for encoding transmission information into coded systematic symbols and at least one parity symbol pair, and maps the coded symbols using a second or higher modulation order before transmission. An interleaver controller performs a control operation of cyclic-shifting the systematic symbols among the symbols coded by the turbo encoder depending on a size of a physical packet to be transmitted, the number of transmission slots, and the modulation order, using an equation of (K×c+k)mod R, and cyclic-shifting redundancy symbols constituting the remaining size of the coded symbols to be transmitted, using an equation of floor{(K×c+k)/D}mod R. An interleaver cyclic-shifts input symbols under the control of the interleaver controller.

Abstract: In one aspect the invention is a method for sequence estimating. The method includes receiving convolutional codes. The method further includes using a lazy Viterbi decoder to decode the convolutional codes. The convolutional codes may be stream convolutional codes. The convolutional codes may also be block convolutional codes. The lazy Viterbi decoder may be used in a software radio environment.

Abstract: A printing device comprises memory storing data in blocks and a processing unit communicating with the memory and being responsive to print jobs. In response to a print job, the processing unit accesses the memory and extracts data therein to be used to complete the print job. The processing unit performs a data block correcting procedure during printing device idle times.

Abstract: Improved error correction techniques and circuitry are provided. The error correction circuitry may be integrated with a programmable logic device (PLD), or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of providing data recovery during extended drop out periods of a high speed serial link with an embedded clock signal.

Abstract: A system, method and data structure for error correction for use in the transmission of content data distribution networks uses a compressed memory, for example a bitmap, to identify portions of transmitted content data files where transmission errors have occurred. The error memory, is used to generate an error status report that is returned to a transmission controller via a low bandwidth back channel, for example the Internet. The information in multiple error status reports is aggregated by the control system of the transmitter and used to re-transmit those portions of previously transmitted content data files that were not properly received due to error. By re-transmitting only the data packets of the transmitted content data files that contain errors, overall transmission speed is increased and bandwidth usage is conserved.

Abstract: Apparatus, system, and method for scalable traceback techniques for channel decoding are described.

Abstract: An output coding apparatus includes a coder for coding an inputted bitstream to an error correction and/or detection code composed of information bits and check bits; and a bitstream assembling section for assembling an outputted bitstream by inserting a synchronization code at any one of a plurality of synchronization code insertion positions previously determined in the outputted bitstream, arranging the information bits at any desired positions of the bitstream, and by arranging the check bits at positions other than the synchronization code insertion positions in the bitstream. Therefore, when the coding apparatus is combined with a resynchronization method using both an error correction and/or detection code and a synchronization code, it is possible to solve a problem caused by pseudo-synchronization or synchronization-loss pull-out or step-out due to erroneous detection of the synchronization code.

Abstract: A method is for detecting and correcting errors for a memory storing at least one code block including information data and control data. The method includes reading and decoding each element of the at least one code block to deliver an information item representative of a number of errors in the at least one code block. The method further includes, when the number of errors exceeds one, modifying a parameter of the read by a chosen value, and performing a reading and decoding of the at least one code block again to obtain a new error information item.

Abstract: AMP (Accelerated Message Passing) decoder adapted for LDPC (Low Density Parity Check) codes. A novel approach is presented by which the LDPC coded signals may be decoded in a more efficient, faster, and less computationally intensive manner. Soft bit information, generated from decoding a higher layer square sub-matrix of a parity check matrix of the LDPC code, is employed to assist in the decoding of other square sub-matrices in subsequent layers. This approach allows the decoding of an LDPC code whose parity check matrix has column weight more than 1 (e.g., 2 or more), thereby allowing a much broader selection of LDPC codes to be employed in various communication systems. This approach also provides much improvement in terms of BER/BLER as a function of Eb/No (or SNR), and it can provide comparable (if not better) performance when performing significantly fewer (e.g., up to 50% fewer) decoding iterations that other approaches.

Abstract: A method for calculating an extended hamming checksum and applying the extended hamming checksum to a data packet, the method comprising forming a packet extended hamming checksum mask, calculating a hamming code, calculating an extended hamming checksum using the packet extended hamming checksum mask and the hamming code, and inserting the extended hamming checksum into the data packet.

Abstract: Methods and systems are provided for decoding. In one exemplary embodiment, the method may include detecting a synchronization code at a position selected from a plurality of synchronization code inserting positions. The plurality of synchronization code inserting positions may be positioned at periodic intervals in an input code string, and the input code string may include a multiplexed code string and information indicative of a delimiter of the multiplexed code string. The information may be arranged just after the multiplexed code string or between the multiplexed code string and a subsequent synchronization code. The method may also include demultiplexing the input code string on the basis of the position of the synchronization code detected by the detecting, to produce kinds of compressed codes. The method may further include decoding the compressed codes to output a reconstructed signal, each of the kinds of compressed codes being a variable length code.

Abstract: Byte or symbol organized linear block codes are optimized in terms of reducing the number of ones in their parity check matrices by means of symbol column transformations carried out by multiplication by non-singular matrices. Each optimized symbol column preferably, and probably necessarily, includes a submatrix which is the identity matrix which contributes to low weight check matrices and also to simplified decoding procedures and apparatus. Since circuit cost and layout area are proportional to the number of Exclusive-OR gates which is determined by the number of ones in the check matrix, it is seen that the reduction procedures carried out in accordance with the present invention solve significant problems that are particularly applicable in the utilization of byte organized semiconductor memory systems. Reduced weight coding systems are also generated in accordance with weight reducing procedures used in conjunction with modified Reed Solomon codes.

Abstract: A method of terminating two or more constituent encoders of a turbo encoder employing a turbo code, comprising the step of: generating tail input bits at each of two or more constituent encoders, including deriving the tail input bits from each of the two or more constituent encoders separately from a contents of shift registers within each of the two or more constituent encoders, after an encoding of information bits by the two or more constituent encoders; puncturing one or more tail output bits such that 1/R output tail bits are transmitted for each of a plurality of trellis branches, wherein R is a turbo code rate employed by the turbo encoder during an information bit transmission. In yet another variation, the step of puncturing the tail output bits further comprises the step of: transmitting, during trellis termination, the tail output bits, only if they are sent from an output branch of one of the two or more constituent encoders that are used during information bit transmission.

Abstract: A method for providing wireless communications between a locomotive control unit (LCU) (14) on board a locomotive (16) and a portable operator control unit (OCU) (12) for use in controlling operation of the locomotive from an off-board location includes calculating a transmit bit error check value for a wireless message. The wireless message includes an explicit sequence number assigned to the message so that the explicit sequence number is implicitly encoded in the transmit bit error check value. The method also includes transmitting an encoded message between the OCU and the LCU with the transmit bit error check value and without the explicit sequence number effective to reduce a total amount information needed to be transmitted compared to a message including the explicit sequence number.