Abstract: An optical sensor device may include a set of optical sensors. The optical sensor device may include a substrate. The optical sensor device may include a multispectral filter array disposed on the substrate. The multispectral filter array may include a first dielectric mirror disposed on the substrate. The multispectral filter array may include a spacer disposed on the first dielectric mirror. The spacer may include a set of layers. The multispectral filter array may include a second dielectric mirror disposed on the spacer. The second dielectric mirror may be aligned with two or more sensor elements of a set of sensor elements.

Abstract: A vertical memory device and a method of fabricating the same are proposed. The vertical memory device includes a gate stack structure in which gates and interlayer insulating layers for insulating the gates are alternately laminated on a substrate and multiple memory cell areas and inter-memory cell areas are divided in a first direction perpendicular to the substrate; a channel structure extending in the first direction from the substrate to penetrate the gate stack structure; and charge storage elements disposed between the gate stack structure and the channel structure and sequentially formed to be embedded in the gate stack structure.

Abstract: A spin orbit torque (SOT) memory device includes a SOT electrode having a spin orbit coupling material. The SOT electrode has a first sidewall and a second sidewall opposite to the first sidewall. The SOT memory device further includes a magnetic tunnel junction device on a portion of the SOT electrode. A first MTJ sidewall intersects the first SOT sidewall and a portion of the first MTJ sidewall and the SOT sidewall has a continuous first slope. The MTJ device has a second sidewall that does not extend beyond the second SOT sidewall and at least a portion of the second MTJ sidewall has a second slope.

Abstract: A hybrid microelectronic substrate may be formed by the incorporation of a high density microelectronic patch substrate within a lower density microelectronic substrate. The hybrid microelectronic substrate may allow for direct flip chip attachment of a microelectronic device having high density interconnections to the high density microelectronic patch substrate portion of the hybrid microelectronic substrate, while allowing for lower density interconnection and electrical routes in areas where high density interconnections are not required.

Abstract: An apparatus comprises a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier between the free and fixed layers, the tunnel barrier directly contacting a first side of the free layer, a capping layer contacting the second side of the free magnetic layer and boron absorption layer positioned a fixed distance above the capping layer.

Abstract: A semiconductor package structure includes an electronic device having an exposed region adjacent to a first surface, a dam surrounding the exposed region of the semiconductor die and disposed on the first surface, the dam having a top surface away from the first surface, an encapsulant encapsulating the first surface of the electronic device, exposing the exposed region of the electronic device. A surface of the dam is retracted from a top surface of the encapsulant. A method for manufacturing the semiconductor package structure is also provided.

Abstract: An insulation film includes a first opening portion in at least one of a cell region and a termination region, and a second opening portion in an interface region. The second opening portion has an opening ratio lower than an opening ratio of the first opening portion. The semiconductor device includes a first impurity layer of a second conductivity type, and a second impurity layer of the second conductivity type. The first impurity layer is disposed on a surface of a semiconductor substrate below the first opening portion. The second impurity layer has impurity concentration lower than impurity concentration of the first impurity layer, and is disposed on the surface of the semiconductor substrate below the second opening portion.

Abstract: A light-emitting device includes a package, a light-emitting element disposed on the package, and a light-transmissive member over the light-emitting element. An upper surface of the light-transmissive member and an upper surface of the package each have a plurality of projections. The light-transmissive member contains particles of light-transmissive first fillers having refractive indices smaller than the refractive index of a matrix of the light-transmissive member. Part of the particles of the first fillers is exposed to the air from the matrix of the light-transmissive member on the upper surface of the light-transmissive member.

Abstract: A display panel includes a first substrate, a second substrate, at least one light-emitting diode, at least one reflective layer, and at least one first spacer layer. The first substrate has a filter layer. The second substrate is opposite to the first substrate. The light-emitting diode is disposed on the second substrate. The reflective layer is located on the first substrate and protrudes toward the second substrate. The first spacer layer is located between the first substrate and the second substrate. The first spacer layer has a first end and a second end, and the first end of the first spacer layer is located between a surface of the reflective layer adjacent to the second substrate and the second substrate.

Abstract: A white organic light emitting device and an organic light emitting display device using the white organic light emitting device stably implement white light in a tandem-type top emission structure through uniform lifespans according to emitted colors of light despite driving of the white organic light emitting device for a long time.

Abstract: A semiconductor device including a substrate having a cell, peripheral, and boundary area; a stack structure on the cell area and including insulating and interconnection layers that are alternately stacked; a molding layer on the peripheral area boundary areas; a selection line isolation pattern extending into the stack structure; a cell channel structure passing through the stack structure; and first dummy patterns extending into the molding layer on the peripheral area, wherein upper surfaces of the first dummy patterns, an upper surface of the selection line isolation pattern, and an upper surface of the cell channel structure are coplanar, and at least one of the first dummy patterns extends in parallel with the selection line isolation pattern or cell channel structure from upper surfaces of the first dummy patterns, the upper surface of the selection line isolation pattern, and the upper surface of the cell channel structure toward the substrate.

Abstract: A light emitting device package includes: a plurality of light emitting structures, each having a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer; a common first electrode extended in parallel with first and second surfaces of the plurality of light emitting structures at a level different from levels of the first and second surfaces while connecting respective first conductivity-type semiconductor layers of the plurality of light emitting structures; a plurality of second electrodes connected to respective second conductivity-type semiconductor layers of the plurality of light emitting structures; a plurality of wavelength converters; and a molded portion having a partition wall structure separating the plurality of wavelength converters from each other, and including a material having a modulus lower than a modulus of the plurality of light emitting structures.

Abstract: The disclosure discloses an array substrate, a method for fabricating the same, a liquid crystal display panel, and a display device, where the array substrate includes: a base substrate; a convex component located on the base substrate; a reflection layer overlying the convex component; a thin film transistor located above a film layer at which the reflection layer is located; a pixel electrode located above a film layer at which the thin film transistor is located; and a planarization layer located between the pixel electrode and the reflection layer.

Abstract: Example embodiments disclose a vertical memory device and method of manufacturing the same. The device may include a plurality of gate electrodes and a plurality of insulation patterns and a channel that penetrates a first gate electrode and a first insulation pattern. The device may have a charge storage structure including a tunnel insulation pattern, a charge trapping pattern, and a blocking pattern that are sequentially stacked from an outer sidewall of a channel. The device may have a buried pattern structure that is surrounded by the tunnel insulation pattern and the charge trapping pattern. The charge trapping pattern may include a first vertically sloped portion having a first thickness in the horizontal direction and a second vertically sloped portion having a second thickness in the horizontal direction, and the first thickness may be less than or equal to the second thickness.

Abstract: A light emitting device includes a semiconductor layer having a light extraction surface and side surfaces. The semiconductor layer includes a cladding layer and an active layer. The cladding layer has the extraction surface and a cladding layer side surface of the side surfaces, the cladding layer side surface being arranged at a first angle to the extraction surface. The active layer has an active layer side surface of the side surfaces, the active layer side surface being arranged at a second angle different from the first angle to the extraction surface.

Abstract: A package structure and a method for forming the same are provided. The package structure includes a die, a first molding surrounding the die, a first redistribution layer (RDL), an interposer disposed over the first RDL, a second molding surrounding the interposer, a first via, and a second RDL. The first RDL includes a first dielectric layer disposed over the die and the first molding, and a first interconnect structure surrounded by the first dielectric layer and electrically connected to the die. The interposer is electrically connected to the die through the first interconnect structure. The first via extends through and within the second molding and is adjacent to the interposer. The second RDL includes a second dielectric layer disposed over the interposer and the second molding, and a second interconnect structure surrounded by the second dielectric layer and electrically connected to the via and the interposer.

Abstract: The semiconductor device includes a first electrode, a second electrode electrically coupled to the first electrode, and a third electrodes electrically coupled to at least one of the first and the second electrode, a first plating deposition portion on the first electrode, a second and a third plating deposition portions formed on the second and the third electrode, respectively. The areas of the second and the third plating deposition portion are smaller than the area of the first plating deposition portion. The periphery length of the third plating deposition portion is longer than the periphery length of the second plating deposition portion.

Abstract: A light-emitting diode structure includes a first type semiconductor layer, a light-emitting layer, a second type semiconductor layer, a reflective layer, and an ohmic contact layer. The light-emitting layer is disposed under the first type semiconductor layer. The second type semiconductor layer is disposed under the light-emitting layer, wherein the second type semiconductor layer includes a plurality of recesses which are recessed from a lower surface of the second type semiconductor layer toward the light-emitting layer. The reflective layer is disposed in the recesses. The ohmic contact layer is disposed under the lower surface of the second type semiconductor layer and surrounds the recesses. The light-emitting diode structure can increase the luminous efficiency greatly.

Abstract: Embodiments of the invention describe low capacitance interconnect structures for semiconductor devices and methods for manufacturing such devices. According to an embodiment of the invention, a low capacitance interconnect structure comprises an interlayer dielectric (ILD). First and second interconnect lines are disposed in the ILD in an alternating pattern. The top surfaces of the first interconnect lines may be recessed below the top surfaces of the second interconnect lines. Increases in the recess of the first interconnect lines decreases the line-to-line capacitance between neighboring interconnects. Further embodiments include utilizing different dielectric materials as etching caps above the first and second interconnect lines. The different materials may have a high selectivity over each other during an etching process. Accordingly, the alignment budget for contacts to individual interconnect lines is increased.

Abstract: A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region and an electrode structure including first and second electrodes alternatingly and vertically stacked on the substrate and having a stair-step structure on the connection region. Each of the first and second electrodes may include electrode portions provided on the cell array region to extend in a first direction and to be spaced apart from each other in a second direction perpendicular to the first direction, an electrode connecting portion provided on the connection region to extend in the second direction and to horizontally connect the electrode portions to each other, and protrusions provided on the connection region to extend from the electrode connecting portion in the first direction and to be spaced apart from each other in the second direction.