Abstract: The present invention provides an organic light emitting device and a fabricating method thereof. The organic light emitting device includes a thin film transistor substrate, a pixel defining layer, a reflective electrode layer, and a plurality of sub-pixels. The pixel defining layer is disposed on the thin film transistor substrate and includes a plurality of via holes; and the plurality of sub-pixels are disposed in the via holes correspondingly. A thin film stand layer is disposed on the thin film transistor substrate and corresponds to a portion of the via holes, causing a reduction in a depth of the portion of the via holes, and a depth of another portion of the via holes is greater than the depth of the portion of the via holes.

Abstract: A light emitting diode includes a first type semiconductor layer, an active layer, a second type semiconductor layer, a patterned electrode layer, a flat layer and a reflective layer. The active layer is disposed on the first type semiconductor layer. The second type semiconductor layer is disposed on the active layer. The second type semiconductor layer includes a first surface and a second surface having a first arithmetic mean roughness. The patterned electrode layer is disposed on the second surface of the second type semiconductor layer. The planarization layer is disposed on the second type semiconductor layer. The planarization layer includes a third surface and a fourth surface. The third surface is in contact with the second surface of the second type semiconductor layer. The fourth surface has a second arithmetic mean roughness that is less than the first arithmetic mean roughness.

Abstract: A light-emitting element includes a light-emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer interposed between the first conductive semiconductor layer and the second conductive semiconductor layer; a first contact electrode and a second contact electrode located on the light-emitting structure, and respectively making ohmic contact with the first conductive semiconductor layer and the second conductive semiconductor layer; an insulation layer for covering a part of the first contact electrode and the second contact electrode so as to insulate the first contact electrode and the second contact electrode; a first electrode pad and a second electrode pad electrically connected to each of the first contact electrode and the second contact electrode; and a radiation pad formed on the insulation layer, and radiating heat generated from the light-emitting structure.

Abstract: A stretchable display device includes a display area having stretchable display units each including first islands on which pixels are disposed and first cut-out grooves between the first islands. A peripheral area is adjacent to the display area, the peripheral area includes stretchable peripheral units each including first lines on which driving circuits are disposed and first opening portions between the first lines. A buffer area is disposed between the display area and the peripheral area. The buffer area includes stretchable buffer units each including second islands, second cut-out grooves between the second islands, second lines connected to the second islands, and second opening portions between the second lines. Shapes of the second cut-out grooves may be different from shapes of the first cut-out grooves, and shapes of the second opening portions may be different from shapes of the first opening portions.

Abstract: Semiconductor devices and methods of fabricating the same are provided. The method includes forming on a substrate an active pattern that protrudes from the substrate and extends in one direction; forming on the active pattern a sacrificial gate structure that extends in a direction intersecting the active pattern; forming on a side surface of the sacrificial gate structure a first spacer including a first portion at a lower level than a top surface of the active pattern and a second portion on the first portion, and reducing a thickness of the second portion of the first spacer.

Abstract: A method of forming a semiconductor device includes attaching a metal foil to a carrier, the metal foil being pre-made prior to attaching the metal foil; forming a conductive pillar on a first side of the metal foil distal the carrier; attaching a semiconductor die to the first side of the metal foil; forming a molding material around the semiconductor die and the conductive pillar; and forming a redistribution structure over the molding material.

Abstract: Methods to form vertically conducting and laterally conducting low-cost resistor structures utilizing dual-resistivity conductive materials are provided. The dual-resistivity conductive materials are deposited in openings in a dielectric layer using a single deposition process step. A high-resistivity ?-phase of tungsten is stabilized by pre-treating portions of the dielectric material with impurities. The portions of the dielectric material in which impurities are incorporated encompass regions laterally adjacent to where high-resistivity ?-W is desired. During a subsequent tungsten deposition step the impurities may out-diffuse and get incorporated in the tungsten, thereby stabilizing the metal in the high-resistivity ?-W phase. The ?-W converts to a low-resistivity ?-phase of tungsten in the regions not pre-treated with impurities.

Abstract: Disclosed are an organic light emitting display device to improve optical efficiency and prevent deterioration in reliability of thin film transistors, and a method of manufacturing the same. The organic light emitting display device includes a mirror wall which is disposed on a substrate such that the mirror wall surrounds a light emitting area of each sub-pixel where a light emitting element is disposed, thus preventing total reflection of light produced in the light emitting element and improving optical efficiency by reflecting light travelling toward a non-emitting area to be directed to the light emitting area.

Abstract: A light-emitting panel includes a plurality of pixels, a plurality of first regulators, and a plurality of second regulators. The plurality of first regulators extends in a first direction and defines each two of the pixels that are adjacent to each other in a second direction orthogonal to the first direction. The plurality of second regulators extends in the second direction and defines each two of the pixels that are adjacent to each other in the first direction. The plurality of pixels at least includes a first pixel and a second pixel that have different lengths in the first direction from each other and share a light-emitting layer. The first pixel and the second pixel are at least adjacent to each other in the first direction with the second regulator being interposed between the first pixel and the second pixel.

Abstract: A display device includes a substrate having flexibility, a transistor having a gate insulating film and further having a semiconductor layer and a gate electrode that sandwich the gate insulating film, the transistor formed in an area where the substrate is bent, and a gate wiring line so formed on the substrate as to be connected to the gate electrode, and the gate electrode has an area that is present in an area where the gate electrode overlaps with the semiconductor layer and is thinner than at least part of the gate wiring line.

Abstract: A semiconductor device wherein a high-side circuit region, a low-side circuit region, and a high-voltage MOS that transmits a signal between the high-side circuit region and the low-side circuit region are provided on one semiconductor substrate, includes: a high-voltage isolation region isolating the high-side circuit region and the low-side circuit region from each other; a trench isolation isolating the high-voltage MOS and the high-voltage isolation region from each other; an N-type diffusion layer provided on an upper surface of the semiconductor substrate in the high-side circuit region and the high-voltage isolation region; and an N-type region provided on both sides of the trench isolation and having an impurity concentration lower than an impurity concentration of the N-type diffusion layer.

Abstract: A method of manufacturing semiconductor device includes providing a radiation emitting semiconductor chip having a first main surface, applying a metallic seed layer to a second main surface opposite the first main surface, galvanically depositing first and second metallic volume regions on the seed layer, depositing an adhesion promoting layer on the volume regions, and applying a casting compound at least between contact points, wherein before the metallic volume regions are galvanically deposited, a dielectric layer is first applied to the seed layer over its entire surface and openings are produced in the dielectric layer by etching, and a material of the metallic volume regions is deposited through the openings of the dielectric layer, wherein the dielectric layer is underetched at boundaries to the openings and the underetches are filled with material of the metallic volume regions during the galvanical depositing of the metallic volume regions.

Abstract: A semiconductor device package includes an electronic component. The electronic component has an active surface, a back surface opposite to the active surface, and a lateral surface connected between the active surface and the back surface. The electronic component has an electrical contact disposed on the active surface. The semiconductor device package also includes a redistribution layer (RDL) contacting the back surface of the electronic component, a first dielectric layer surrounding the electrical contact on the active surface of the electronic component, and a second dielectric layer surrounding the lateral surface of the electronic component and the first dielectric layer. The second dielectric layer has a first sidewall in contact with the lateral surface of the electronic component and a second sidewall opposite to the first sidewall. The second sidewall of the second dielectric layer has a first portion proximal to the RDL and a second portion distal from the RDL.

Abstract: Embodiments described herein relate generally to one or more methods for forming an interconnect structure, such as a dual damascene interconnect structure comprising a conductive line and a conductive via, and structures formed thereby. In some embodiments, an interconnect opening is formed through one or more dielectric layers over a semiconductor substrate. The interconnect opening has a via opening and a trench over the via opening. A conductive via is formed in the via opening. A nucleation enhancement treatment is performed on one or more exposed dielectric surfaces of the trench. A conductive line is formed in the trench on the one or more exposed dielectric surfaces of the trench and on the conductive via.

Abstract: Some embodiments include a memory device having a vertical stack of alternating insulative levels and conductive levels. Memory cells are along the conductive levels. The conductive levels have control gate regions which include a first vertical thickness, have routing regions which include a second vertical thickness that is less than the first vertical thickness, and have tapered transition regions between the first vertical thickness and the second vertical thickness. Charge-blocking material is adjacent to the control gate regions. Charge-storage material is adjacent to the charge-blocking material. Dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the vertical stack and is adjacent to the dielectric material. The memory cells include the control gate regions, and include regions of the charge-blocking material, the charge-storage material, the dielectric material and the channel material.

Abstract: A display apparatus includes a substrate, a light-emitting diode (“LED”) provided above the substrate, an insulating layer provided above the LED, and a wire grid polarizer (“WGP”) provided above the insulating layer.

Abstract: A display device is disclosed. In one aspect, the display device includes a substrate including a display area, the display area including a plurality of pixels configured to display an image and a pad area adjacent to the pad area and configured to transfer electrical signals. At least a portion of the pad area is bendable. The display device also includes an insulating layer formed over the substrate and including a bending groove in the pad area. The bending groove includes a sidewall. A plurality of peripheral wires is formed over the insulating layer, and a cutoff portion is connected to the sidewall and disposed between adjacent peripheral wires.

Abstract: A display device in which a display area and a non-display area are defined, the display device including a wiring substrate, the wiring substrate including: a base substrate; a first thin film transistor disposed on the base substrate, located in the non-display area, and including a first gate pattern, a first semiconductor pattern disposed on the first gate pattern, a first source pattern disposed on the first semiconductor pattern, and a first drain pattern disposed on the first semiconductor pattern and spaced apart from the first source pattern; and a second thin film transistor disposed on the base substrate and located in the display area. A first channel width of the first thin film transistor is greater than a first overlap length of the first gate pattern, the first semiconductor pattern, and the first drain pattern.

Abstract: A semiconductor device includes a substrate, a FinFET, and an insulating structure. The FinFET includes a fin, a gate electrode, and a gate dielectric layer. The fin is over the substrate. The gate electrode is over the fin. The gate dielectric layer is between the gate electrode and the fin. The insulating structure is over the substrate, adjacent the fin, and has a top surface lower than a top surface of the fin. The top surface of the insulating structure has opposite first and second edge portions and an intermediate portion between the first and second edge portions. The first edge portion of the top surface of the insulating structure is lower than the intermediate portion of the top surface of the insulating structure.

Abstract: A transistor comprises semiconductor material that is generally L-shaped or generally mirror L-shaped in at least one straight-line vertical cross-section thereby having an elevationally-extending stem and a base extending horizontally from a lateral side of the stem above a bottom of the stem. The semiconductor material of the stem comprises an upper source/drain region and a channel region there-below. The transistor comprises at least one of (a) and (b), where (a): the semiconductor material of the stem comprises a lower source/drain region below the channel region, and (b): the semiconductor material of the base comprises a lower source/drain region. A gate is operatively laterally adjacent the channel region of the stem. Other embodiments are disclosed, including arrays of memory cells individually comprising a capacitor and an elevationally-extending transistor. Methods are disclosed.